Methods and apparatuses having a voltage generator with an adjustable voltage drop for representing a voltage drop of a memory cell and/or a current mirror circuit and replica circuit
View Patent ↗Apparatus and methods utilize a replica circuit to generate a voltage for programming of a memory cell, such as a memory cell of a phase-change memory (PCM). Current passing through a circuit including the memory cell to be programmed is mirrored in a scaled or unscaled manner, and provided as an input to the replica circuit. The replica circuit represents voltage drops that should be encountered when programming the memory cell. An input voltage is also provided to the replica circuit, which affects the voltage drop within the replica circuit that represents the voltage drop of the cell. The voltage drop across the replica circuit can then be mirrored and provided to bias the circuit including the memory cell.
1. A method of programming a memory cell, comprising:
determining a voltage drop of a programming path to one or more memory cells of an array, the one or more memory cells each storing one or more logic states;
determining a voltage for a voltage source based at least in part on the determined voltage drop of the programming path;
applying a programming voltage to the one or more memory cells of the array based at least in part on the determined voltage, wherein the one or more logic states are based at least in part on a modulation of the determined voltage;
mirroring a current received by the voltage source using a current mirroring circuit;
transmitting a replica voltage based at least in part on voltage drops of the programming path to the one or more memory cells of the array and the mirrored current; and
setting the programming voltage to a nonzero voltage at a first time using a source follower circuit connected to the current mirroring circuit and a voltage biasing circuit.
2. The method of claim 1 , wherein the modulation of the determined voltage is based at least in part on:
adjusting the determined voltage at a modulator; and
applying the adjusted voltage to the one or more memory cells.
3. The method of claim 2 , further comprising:
ramping an input voltage signal received by the modulator, wherein the adjusted voltage is based at least in part on the ramped input voltage signal.
4. The method of claim 3 , wherein ramping the input voltage signal comprises:
ramping the input voltage signal at a slope less than 1 volt per 20 nanoseconds to produce a crystalline state for at least one of the one or more memory cells, or
ramping the input voltage signal at a slope greater than 1 volt per 20 nanoseconds to produce an amorphous state for at least one of the one or more memory cells.
5. The method of claim 2 , further comprising:
setting the programming voltage to the determined voltage by short-circuiting the modulator.
6. The method of claim 1 , wherein determining the voltage for the voltage source comprises:
applying a second voltage to a replica circuit that comprises a resistance that is based at least in part on the resistance of the programming path to the one or more memory cells.