IP Library Granted Patent US 10,157,644
Granted Patent B1
US 10,157,644 · App. 15/671,317 · Granted Dec 18, 2018

Methods and apparatus for generation of voltages

Inventors: Agostino Macerola (San Benedetto dei Marsi, IT); Marco-Domenico Tiburzi (Avezzano, IT); Stefano Perugini (Popoli, IT)
Assignee: Micron Technology, Inc.
G11C5/145G05F3/16G06F1/3203G06F1/3275G11C5/147
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 10,157,644
App. No.
15/671,317
Filed
Aug 8, 2017
Granted
Dec 18, 2018
Kind
B1
Art Unit
2842
USPC
327/143
Abstract

Methods of operating a voltage generation circuit, and apparatus configured to perform such methods, include applying a clock signal to an input of a voltage driver of a stage of the voltage generation circuit, connecting the voltage driver output to a first voltage node configured to receive a first voltage when the clock signal has a particular logic level and a voltage level of the voltage driver output is less than a threshold, connecting the voltage driver output to a second voltage node configured to receive a second voltage greater than the first voltage when the clock signal has the particular logic level and the voltage level of the voltage driver output is greater than the threshold, and connecting the voltage driver output to a third voltage node configured to receive a third voltage less than the first voltage when the clock signal has a different logic level.

Claims (22)

1. A voltage generation system, comprising:

a first voltage generation circuit, the first voltage generation circuit comprising:

an input;

an output; and

a first plurality of stages between the input and the output of the first voltage generation circuit, wherein a stage of the first plurality of stages comprises:

a first voltage isolation device;

a first voltage driver having a first input connected to a first voltage node configured to receive a first voltage, a second input connected to a second voltage node configured to receive a second voltage less than the first voltage, and a third input configured to receive a first clock signal;

a first stage capacitance having a first electrode connected to an output of the first voltage driver and a second electrode connected to the first voltage isolation device;

wherein the first voltage driver is configured to connect its output to the first voltage node when the clock signal has a particular logic level; and

wherein the first voltage driver is further configured to connect its output to the second voltage node when the clock signal has a different logic level; and

a second voltage generation circuit, the second voltage generation circuit comprising:

an input connected to the output of the first voltage generation circuit;

an output; and

a second plurality of stages between the input and the output of the second voltage generation circuit, wherein a stage of the second plurality of stages comprises:

a second voltage isolation device;

a second voltage driver having a first input connected to a first voltage node configured to receive the first voltage, a second input connected to the output of the first voltage generation circuit, a third input connected to a third voltage node configured to receive the second voltage, and a fourth input configured to receive a second clock signal;

a second stage capacitance having a first electrode connected to an output of the second voltage driver and a second electrode connected to the second voltage isolation device;

wherein the second voltage driver is configured to connect its output to its first voltage node when the second clock signal has a particular logic level and a voltage level of its output is less than a threshold;

wherein the second voltage driver is further configured to connect its output to the output of the first voltage generation circuit when the second clock signal has its particular logic level and the voltage level of its output is greater than the threshold; and

wherein the second voltage driver is further configured to connect its output to its third voltage node when the second clock signal has a different logic level.

2. The voltage generation system of claim 1 , wherein the first voltage generation circuit and the second voltage generation circuit are each configured to generate an increasing voltage at their respective output.

3. The voltage generation system of claim 1 , wherein the first voltage generation circuit is configured to generate an increasing voltage at its respective output, and wherein the second voltage generation circuit is configured to generate a decreasing voltage at its output.

Assignments (7)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050709/0838 →
RELEASE OF SECURITY INTEREST Recorded Jul 20, 2018
From: U.S. BANK NATIONAL ASSOCIATION, AS AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 046597/0333 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
SUPPLEMENT NO. 6 TO PATENT SECURITY AGREEMENT Recorded Nov 1, 2017
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 044653/0333 →
SUPPLEMENT NO. 6 TO PATENT SECURITY AGREEMENT Recorded Nov 1, 2017
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 044348/0253 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 8, 2017
From: MACEROLA, AGOSTINO; TIBURZI, MARCO-DOMENICO; PERUGINI, STEFANO
To: MICRON TECHNOLOGY, INC.
Reel/Frame 043227/0799 →