IP Library Granted Patent US 10,489,257
Granted Patent B2
US 10,489,257 · App. 15/671,774 · Granted Nov 26, 2019

Replaceable memory

Inventors: Ananda C. S. Mahesh (Cedar Park, TX); Gregory P. Shogan (Round Rock, TX)
Assignee: Micron Technology, Inc.
G06F11/2094G06F11/1662G06F11/2017G06F11/2092G06F2201/805
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Quick Facts
Patent No.
US 10,489,257
App. No.
15/671,774
Granted
Nov 26, 2019
Kind
B2
Abstract

The present disclosure includes apparatuses comprising replaceable memory. An example apparatus may include a controller and a memory package coupled to the controller and including a plurality of memory dies. At least one of the memory package and the controller may be a replaceable unit that is removable from the apparatus and replaceable with a different replaceable unit while maintaining operation of the apparatus.

Claims (49)

1. An apparatus, comprising:

a controller; and

a memory package coupled to the controller, the memory package comprising a plurality of memory dies and located on a system board of the apparatus;

wherein at least one of the memory package and the controller is a replaceable unit that is removable from the system board of the apparatus and replaceable with a different replaceable unit while maintaining operation of the apparatus, and wherein the at least one of the memory package and the controller is removable from the apparatus without removing the system board from the apparatus.

2. The apparatus of claim 1 , wherein:

the memory package is one of a plurality of memory packages of the apparatus; and

each one of the plurality of memory packages is a replaceable unit such that, subsequent to a failure of one or more of the plurality of memory packages, the one or more of the plurality of memory packages is replaced to maintain a same number of non-failed memory packages despite the failure.

3. The apparatus of claim 1 , wherein:

the controller is one of a plurality of controllers of the apparatus that are coupled to the memory package; and

each one of the plurality of controllers is a replaceable unit such that, subsequent to a failure of one or more of the plurality of controllers, a non-failed one of the plurality of controllers is configured to continue serving the memory package such that the operation of the apparatus is maintained despite the failure.

4. The apparatus of claim 1 , wherein the plurality of memory dies comprise non-volatile memory cells.

5. An apparatus, comprising:

a plurality of controllers; and

a plurality of memory packages coupled to the plurality of controllers and located on a system board;

wherein at least one of the plurality of memory packages comprises a plurality of memory dies; and

wherein at least one of the plurality of memory packages and at least one of the plurality of controllers is a replaceable unit that is removable from the system board of the apparatus and replaceable with a different replaceable unit while maintaining operation of the apparatus, and wherein the at least one of the plurality of memory packages is removable from the apparatus without removing the system board from the apparatus.

6. The apparatus of claim 5 , wherein, responsive to a failure of one of the plurality of controllers:

the failed one of the plurality of controllers is replaced with a different replaceable unit, and

a non-failed one of the plurality of controllers is configured to continue serving the plurality of memory packages such that the operation is maintained despite the failure.

7. The apparatus of claim 5 , wherein the plurality of controllers are coupled to each other via an inter-controller messaging bus.

8. The apparatus of claim 5 , wherein the plurality of controllers are coupled to the plurality of memory packages and configured to serve the plurality of memory packages via a non-volatile memory express (NVMe) interface.

9. The apparatus of claim 5 , wherein the plurality of controllers are configured to protect data stored on the plurality of memory packages by providing at least one of:

a redundant array of independent nodes (RAIN); and

error correction coding (ECC).

10. The apparatus of claim 5 , wherein at least one of the memory dies comprises storage class memory (SCM).

11. The apparatus of claim 5 , wherein each one of the memory packages is a NAND flash memory package.

12. An apparatus, comprising:

a plurality of controllers; and

a plurality of system boards coupled to the plurality of controllers and comprising a plurality of memory packages;

wherein at least one of the plurality of system boards, at least one of the plurality of controllers, and at least one of the plurality of memory packages is a replaceable unit that is removable from the apparatus and replaceable with a different replaceable unit while maintaining operation of the apparatus, and wherein at least one of the plurality of memory packages is removable from a particular one of the plurality of system boards on which it resides without removing the particular one of the plurality of system boards from the apparatus.

13. The apparatus of claim 12 , wherein the replaceable unit is removable from the apparatus and replaceable with a different replaceable unit responsive to a failure of the replaceable unit such that, subsequent to a replacement of the failed replaceable unit, the apparatus is operable along with the different replaceable unit.

14. The apparatus of claim 12 , wherein a non-failed memory package located on a failed one of the plurality of system boards is reusable on a non-failed one of the plurality of system boards.

15. The apparatus of claim 12 , wherein the plurality of controllers are configured to protect data stored on the plurality of memory packages via at least one of:

a redundant array of independent disks (RAID),

a redundant array of independent nodes (RAIN); and

error correction coding (ECC).

16. The apparatus of claim 12 , wherein the plurality of controllers are coupled to a host, wherein the host is configured to provide a data protection scheme across the plurality of system boards such that data stored in a failed one of the plurality of system boards is restorable.

17. An apparatus, comprising:

a host;

a memory system coupled to the host and comprising:

a plurality of controllers; and

a plurality of non-volatile memory (NVM) packages coupled to the number of controllers via a bus; and

wherein at least one of the plurality of NVM packages of the memory system is a replaceable unit that is physically removable from a system board of the memory system and replaceable with a different NVM package while maintaining operation of the memory system, and wherein the at least one of the plurality of NVM packages of the memory system is physically removable from the system board without removing the system board from the memory system.

18. The apparatus of claim 17 , wherein at least one of the plurality of controllers is a replaceable unit that is removable from the apparatus and replaceable with a different replaceable unit while maintaining operation of the memory system.

19. The apparatus of claim 17 , wherein the memory system is a solid state drive (SSD).

20. The apparatus of claim 17 , wherein the bus is an ONFI compliant bus.

21. The apparatus of claim 17 , wherein the memory system comprises a plurality of power supplies, and wherein at least one of the plurality of power supplies is a replaceable unit that is removable from the apparatus and replaceable with a different replaceable unit.

22. The apparatus of claim 17 , wherein the plurality of memory packages are spread across a plurality of distinct system boards, and wherein at least one of the system boards is replaceable unit that is removable from the apparatus and replaceable with a different replaceable unit.

23. The apparatus of claim 17 , wherein data received from the host is redundantly stored in at least two of the plurality of NVM packages.

Assignments (7)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050709/0838 →
RELEASE OF SECURITY INTEREST Recorded Jul 20, 2018
From: U.S. BANK NATIONAL ASSOCIATION, AS AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 046597/0333 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
SUPPLEMENT NO. 6 TO PATENT SECURITY AGREEMENT Recorded Nov 1, 2017
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 044348/0253 →
SUPPLEMENT NO. 6 TO PATENT SECURITY AGREEMENT Recorded Nov 1, 2017
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 044653/0333 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 8, 2017
From: MAHESH, ANANDA C. S.; SHOGAN, GREGORY P.
To: MICRON TECHNOLOGY, INC.
Reel/Frame 043232/0772 →
Continuity (1)
Related Publication 20190050305A1 · Feb 14, 2019