Swap operations in memory

1. A method comprising:

performing a swap operation, comprising:

swapping a first element stored in a first group of memory cells coupled to a first sense line and to a number of access lines of an array of memory cells with a second element stored in a second group of memory cells coupled to a second sense line and to the number of access lines, such that subsequent to the swapping, the first element is stored in the second group of memory cells and the second element is stored in the first group of memory cells;

wherein the first element and the second element are a first element pair; and

wherein performing the swap operation comprises swapping multiple element pairs in parallel, with each respective one of the multiple element pairs being stored in memory cells coupled to different sense lines.

2. The method of claim 1 , wherein, prior to the swapping, the first element is stored as a first bit-vector in the first group of memory cells, with each memory cell in the first group of memory cells storing a respective bit of the first bit-vector.

3. The method of claim 2 , wherein, prior to swapping, the second element is stored as a second bit-vector in the second group of memory cells, with each memory cell in the second group of memory cells storing a respective bit of the second bit-vector.

4. The method of claim 3 , wherein, subsequent to the swapping, the first bit-vector is stored in the second group of memory cells and the second bit-vector is stored in the first group of memory cells.

5. The method of claim 1 , further comprising swapping the multiple element pairs in parallel without activating a column decode signal to transfer data from sense lines onto input/output lines.

6. The method of claim 1 , wherein the first element is a first value and the second element is a second value and wherein performing the swap operation results in storing the first value in the second group of memory cells and storing the second value in the first group of memory cells.

7. An apparatus comprising:

a host; and

a memory device coupled to the host and configured to control sensing circuitry to swap, in parallel, a plurality of first elements stored in respective groups of cells corresponding to first respective different columns of an array with a respective plurality of second elements stored in respective groups of cells corresponding to second respective different columns;

wherein swapping the plurality of first elements with the respective plurality of second elements comprises performing a number of iterations of operations, and wherein the number of iterations is equal to an element width of the first and the second plurality of elements.

8. The apparatus of claim 7 , wherein the memory device comprises a controller configured to control the sensing circuitry.

9. The apparatus of claim 7 , wherein the host comprises a processor, and wherein the memory device is configured to perform the swapping, in parallel, without using the processor.

10. The apparatus of claim 7 , wherein in the respective groups of cells corresponding to first respective different columns of the array and the respective groups of cells corresponding to second respective different columns are coupled to a same group of access lines of the array.

11. The apparatus of claim 7 , wherein the same group of access lines of the array comprise adjacent access lines.

12. The apparatus of claim 7 , including using a controller of the memory device to perform the number of iterations of operations by storing a particular bit from each of the plurality of first elements in memory cells of the plurality of second groups of memory cells and storing a particular bit from each of the plurality of second elements in memory cells of the plurality of first groups of memory cells.

13. The apparatus of claim 7 , wherein the memory device is configured to swap the plurality of first elements with the respective plurality of second elements without activating a column decode signal to transfer data from sensing circuitry onto input/output lines.

14. An apparatus comprising:

a host; and

a memory device coupled to the host and configured to cause:

a first element stored in a first group of cells corresponding to a first column of an array to be stored in a second group of cells; and

a second element stored ire a second group of cells corresponding to a second column of the array to be stored in the first group of memory cells by controlling sensing circuitry to perform a number AND operations, OR operations, INVERT operations, and shift operations; and

wherein the sensing circuitry comprises:

a first sense amplifier coupled to a first compute component and corresponding to the first column of the array; and

a second sense amplifier coupled to a second compute component and corresponding to the second column of the array;

wherein the first element and the second element comprise a first element pair to be swapped, and wherein the memory device is configured to swap multiple other element pairs in parallel.

15. The apparatus of claim 14 , wherein the first and second compute components comprise transistors formed on pitch with the memory cells of their corresponding columns of the array.

16. The apparatus of claim 14 , wherein the first and second columns are adjacent columns.

17. The apparatus of claim 14 , wherein the memory device comprises a controller coupled to the array.

18. The apparatus of claim 14 , wherein the host comprises an external processor coupled to the memory device.

19. The apparatus of claim 14 , wherein each of the multiple other element pairs comprise elements stored in cells coupled to adjacent columns of the array.