Virtual ground sensing circuitry and related devices, systems, and methods for crosspoint ferroelectric memory
A virtual ground sensing circuit includes a sense circuit configured to compare a reference voltage potential to a sense node voltage potential, and virtual ground circuitry operably coupled to the sense circuit. The virtual ground circuitry is configured to provide a virtual ground at a first bias voltage potential to a conductive line operably coupled to a selected ferroelectric memory cell, and discharge the conductive line to the sense node responsive to the selected ferroelectric memory cell changing from a first polarization state to a second polarization state. A method includes applying a second bias voltage potential to another conductive line operably coupled to the selected ferroelectric memory cell, and comparing a sense node voltage potential to a reference voltage potential. Electrical systems and computing devices include virtual ground sensing circuits.
1. A virtual ground sensing circuit, comprising:
an operational amplifier comprising a non-inverting input, an inverting input, and an amplifier output;
a follower circuit including an n-MOS transistor and a p-MOS transistor, an input of the follower circuit including a gate of the n-MOS transistor operably coupled to a gate of the p-MOS transistor, and an output of the follower circuit including a source of the n-MOS transistor operably coupled to a source of the p-MOS transistor, the output of the follower circuit operably coupled to the inverting input of the operational amplifier;
a comparator configured to compare a sense node voltage at a drain of one of the n-MOS transistor and the p-MOS transistor to a reference voltage potential; and
another comparator configured to compare another sense node voltage at a drain of the other of the n-MOS transistor and the p-MOS transistor to another reference voltage potential.
2. The virtual ground sensing circuit of claim 1 , wherein a drain of the other of the n-MOS transistor and the p-MOS transistor is operably coupled to a power supply voltage potential.
3. The virtual ground sensing circuit of claim 1 , wherein the output of the follower circuit is operably coupled to a conductive line decoder configured to selectively operably couple the output of the follower circuit to one of a plurality of conductive lines of a memory cell array.
4. The virtual ground sensing circuit of claim 1 , wherein the comparator is configured to compare a drain voltage potential of the p-MOS transistor to the reference voltage potential.
5. The virtual ground sensing circuit of claim 1 , wherein the sense node has a sense node capacitance.
6. The virtual ground sensing circuit of claim 5 , wherein the sense node capacitance includes a parasitic capacitance.
7. The virtual ground sensing circuit of claim 1 , wherein the operational amplifier is an operational transconductance amplifier.
8. A virtual ground sensing circuit, comprising:
an operational amplifier comprising a non-inverting input, an inverting input, and an amplifier output;
a follower circuit including an n-MOS transistor and a p-MOS transistor, an input of the follower circuit including a gate of the n-MOS transistor operably coupled to a gate of the p-MOS transistor, and an output of the follower circuit including a source of the n-MOS transistor operably coupled to a source of the p-MOS transistor, the output of the follower circuit operably coupled to the inverting input of the operational amplifier; and
a comparator configured to compare a sense node voltage at a drain of one of the n-MOS transistor and the p-MOS transistor to a reference voltage potential;
wherein the drain of the one of the n-MOS transistor and the p-MOS transistor is operably coupled to a power supply voltage potential through a transistor configured to isolate the drain of the one of the n-MOS transistor and the p-MOS transistor from the power supply voltage potential during a sense operation.
9. The virtual ground sensing circuit claim 8 , wherein a drain of the other of the n-MOS transistor and the p-MOS transistor is operably coupled to a power supply voltage potential.
10. The virtual ground sensing circuit of claim 8 , wherein the output of the follower circuit is operably coupled to a conductive line decoder configured to selectively operably couple the output of the follower circuit to one of a plurality of conductive lines of a memory cell array.
11. The virtual ground sensing circuit of claim 8 , wherein the comparator is configured to compare a drain voltage potential of the p-MOS transistor to the reference voltage potential.
12. The virtual ground sensing circuit of claim 8 , wherein the sense node has a sense node capacitance.
13. The virtual ground sensing circuit of claim 12 , wherein the sense node capacitance includes a parasitic capacitance.
14. The virtual ground sensing circuit of claim 8 , wherein the operational amplifier is an operational transconductance amplifier.
15. A virtual ground sensing circuit, comprising:
an operational amplifier comprising a non-inverting input, an inverting input, and an amplifier output;
a follower circuit including an n-MOS transistor and a p-MOS transistor, an input of the follower circuit including a gate of the n-MOS transistor operably coupled to a gate of the p-MOS transistor, and an output of the follower circuit including a source of the n-MOS transistor operably coupled to a source of the p-MOS transistor, the output of the follower circuit operably coupled to the inverting input of the operational amplifier;
a comparator configured to compare a sense node voltage at a drain of one of the n-MOS transistor and the p-MOS transistor to a reference voltage potential; and
one or more other comparators configured to compare the sense node voltage to one or more other reference voltage potentials.
16. The virtual ground sensing circuit of claim 15 , further comprising a latch network configured to store a digital value of a multi-bit digital signal that corresponds to a data state of a selected memory cell operably coupled to a conductive line.
17. The virtual ground sensing circuit of claim 16 , wherein the latch network is configured to be clocked by an output of the comparator.
18. A virtual ground sensing circuit, comprising:
an operational amplifier comprising a non-inverting input, an inverting input, and an amplifier output;
a follower circuit including an n-MOS transistor and a p-MOS transistor, an input of the follower circuit including a gate of the n-MOS transistor operably coupled to a gate of the p-MOS transistor, and an output of the follower circuit including a source of the n-MOS transistor operably coupled to a source of the p-MOS transistor, the output of the follower circuit operably coupled to the inverting input of the operational amplifier;
a comparator configured to compare a sense node voltage at a drain of one of the n-MOS transistor and the p-MOS transistor to a reference voltage potential; and
a digital to analog converter (DAC) configured to provide the reference voltage potential to the comparator, wherein a multi-bit digital signal swept from a low digital value to a high digital value is applied to an input of the DAC during a sense operation.
19. The virtual ground sensing circuit of claim 18 , further comprising a latch network configured to store a digital value of the multi-bit digital signal that corresponds to a data state of a selected memory cell operably coupled to a conductive line.
20. The virtual ground sensing circuit of claim 19 , wherein the latch network is configured to be clocked by an output of the comparator.