Low-temperature atomic layer deposition of boron nitride and BN structures
Methods of the disclosure include a BN ALD process at low temperatures using a reactive nitrogen precursor, such as thermal N 2 H 4 , and a boron containing precursor, which allows for the deposition of ultra thin (less than 5 nm) films with precise thickness and composition control. Methods are self-limiting and provide saturating atomic layer deposition (ALD) of a boron nitride (BN) layer on various semiconductors and metallic substrates.
1. A method for atomic layer deposition (ALD) of boron nitride, the method comprising:
placing a 2-dimensional semiconductor substrate in an ALD reactor, the 2-dimensional semiconductor substrate comprising highly ordered pyrolytic graphite (HOPG);
heating the substrate to a deposition temperature of about 350° C. or less; and
sequentially exposing the substrate to a reactive nitrogen containing precursor and a boron containing precursor.
2. The method of claim 1 , wherein the reactive nitrogen containing precursor comprises hydrazine (N 2 H 4 ).
3. The method of claim 2 , wherein the boron containing precursor comprises one of BCl 3 , BBr 3 , BF 3 , B 2 H 6 , borazine (BH) 3 (NH) 3 , tris(dimethylamino)borane (TDMAB) and organometallic boron compounds.
4. The method of claim 1 , wherein the boron containing precursor comprises one of BCl 3 , BBr 3 , BF 3 , B 2 H 6 , borazine (BH) 3 (NH) 3 , tris(dimethylamino) borane (TDMAB) and organometallic boron compounds.
5. The method of claim 1 , wherein the substrate comprises a metal interconnect.
6. The method of claim 1 , wherein the substrate comprises a ceramic.
7. The method of claim 1 , comprising a plurality of sequential exposures at ˜350° C. or less followed by a plurality of sequential exposures at ˜400° C.
8. The method of claim 1 , wherein ˜350° C. or less comprises temperatures below 350° C. sufficient to react the nitrogen containing precursor and a boron containing precursor.
9. A semiconductor device, the device comprising:
a 2-dimensional semiconductor substrate comprising highly ordered pyrolytic graphite (HOPG);
a thin, uniform and pin-hole free interfacial layer of boron nitride; and
a dielectric deposited on the interfacial layer.
10. The device of claim 9 , wherein the dielectric comprises one of Al 2 0 3 , Hf 0 2 , Zr 0 2 , or HfZrO.
11. The device of claim 9 , wherein the dielectric is a gate oxide material.
12. The device of claim 9 , wherein the layer of boron nitride has a thickness of approximately 0.5 nm.