IP Library Granted Patent US 10,432,363
Granted Patent B2
US 10,432,363 · App. 15/674,134 · Granted Oct 1, 2019

Page health prediction using product codes decoder in NAND flash storage

Inventors: Naveen Kumar (San Jose, CA); Aman Bhatia (San Jose, CA); Yi-Min Lin (San Jose, CA)
Assignee: SK hynix Inc.
H04L1/203G06F11/076G06F11/1012G11C11/5642G11C16/349G11C29/021G11C29/028G11C29/50004G11C29/52G11C16/0483G11C29/56008G11C2029/0409G11C2029/0411G11C2029/5004
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Quick Facts
Patent No.
US 10,432,363
App. No.
15/674,134
Granted
Oct 1, 2019
Kind
B2
Abstract

An apparatus of a memory system and an operating method thereof includes: a plurality of memory devices; and a controller including a decoder and a BER predictor, coupled with the plurality of memory devices, configured to perform a decoding iteration includes to conduct NAND read and generate NAND data; decode in accordance with the NAND data and generate decoder information by the decoder; predict a BER in accordance with at least the decode information by the BER predictor; and evaluate the predicted BER and generate evaluation result by the BER predictor.

Claims (37)

1. An operating method of a memory system comprising:

performing

reading data from a page in a NAND memory of the memory system to generate a set of codewords;

starting to decode the set of codewords and generating decoder information therefrom, the decoder information including information generated before completing the decode operation in a current iteration including a number of codewords not successfully decoded in each past iteration and during a portion of the current iteration;

predicting a bit error rate (BER) of the page before completing the decode operation in the current iteration in accordance with at least the decoder information; and

evaluating the predicted BER and generating an evaluation result to determine whether to complete the decode operation in the current iteration, and when it is determined to complete the decode operation in the current iteration, further determine a type of decoding to be used in completing the decode operation.

2. The method of claim 1 wherein the reading of data from the page in the NAND memory is performed according to select NAND read settings.

3. The method of claim 1 wherein the set of codewords are generated using an error control coding scheme.

4. The method of claim 1 wherein the type of decoding is determined from among at least hard decoding and soft decoding.

5. The method of claim 1 wherein the decoder information includes a product code.

6. The method of claim 1 wherein the predicting of the BER of the page in accordance with at least the decoder information is performed again after completing the decode operation in the current iteration.

7. The method of claim 1 wherein the evaluation result includes an indication of whether another complete or partial iteration is to be performed, the partial iteration not including the reading.

8. The method of claim 1 wherein the evaluation result includes an indication that another iteration is not to be performed.

9. The method of claim 7 further comprising: adjusting a read setting according to at least the predicted BER, and repeating the iteration when the evaluation result indicates that another complete iteration is to be performed.

10. The method of claim 7 wherein, based on the evaluation result, another partial iteration is performed to generate updated decoder information, update the BER prediction, and re-evaluate the updated BER prediction.

11. An apparatus of a memory system comprising:

a memory device; and

a controller including a decoder and a BER predictor, coupled with the memory device, the controller configured to

read data from a page in the memory device to generate a set of codewords;

start to decode the set of codewords using the decoder and generate decoder information therefrom, the decoder information including information generated before completing the decode operation in a current iteration including a number of codewords not successfully decoded in each past iteration and during a portion of the current iteration;

predict a bit error rate (BER) of the page before completing the decode operation in the current iteration in accordance with at least the decode information, using the BER predictor; and

evaluate the predicted BER and generate an evaluation result to determine whether to complete the decode operation in the current iteration, using the BER predictor, and when it is determined to complete the decode operation in the current iteration, further determine a type of decoding to be used in completing the decode operation.

12. The apparatus of claim 11 wherein the read of the data from the page in the memory device is performed according to select read settings, and the set of codewords are generated using an error control coding scheme.

13. The apparatus of claim 11 wherein the type of decoding is determined from among at least hard decoding and soft decoding.

14. The apparatus of claim 11 wherein the decoder information includes a product code.

15. The apparatus of claim 11 wherein the controller is further configured to predict the BER again, using the BER predictor, after completing the decode operation in the current iteration.

16. The apparatus of claim 11 wherein the evaluation result includes an indication of whether another complete or partial iteration is to be performed, the partial iteration not including the read operation.

17. The apparatus of claim 11 wherein the evaluation result includes an indication that another iteration is not to be performed.

18. The apparatus of claim 11 wherein the controller is further configured to adjust a read setting according to at least the predicted BER, and repeat the iteration when the evaluation result indicates that another complete iteration is to be performed.

19. The apparatus of claim 16 wherein the controller is further configured to perform another partial iteration, based on the evaluation result, to generate updated decoder information, update the BER prediction, and re-evaluate the updated BER prediction.

20. A memory system comprising:

a processor;

a tangible computer readable storage medium coupled to the processor, embedding the non-transitory computer program product executed by the processor, including computer instructions for:

reading data from a page in a NAND memory of the memory system to generate a set of codewords;

starting to decode the set of codewords and generating decoder information therefrom, the decoder information including information generated before completing the decode operation in a current iteration including a number of codewords not successfully decoded in each past iteration and during a portion of the current iteration;

predicting a bit error rate (BER) of the page before completing the decode operation in the current iteration in accordance with at least the decoder information; and

evaluating the predicted BER and generating an evaluation result to determine whether to complete the decode operation in the current iteration, and when it is determined to complete the decode operation in the current iteration, further determine a type of decoding to be used in completing the decode operation.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 15, 2017
From: SK HYNIX MEMORY SOLUTIONS INC.
To: SK HYNIX INC.
Reel/Frame 044899/0443 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 10, 2017
From: KUMAR, NAVEEN; BHATIA, AMAN
To: SK HYNIX MEMORY SOLUTIONS INC.
Reel/Frame 043262/0760 →
Continuity (2)
Provisional Application 62374692 · Aug 12, 2016
Related Publication 20180048434A1 · Feb 15, 2018