Charge trap structure with barrier to blocking region
Various embodiments, disclosed herein, include methods and apparatus having charge trap structures, where each charge trap structure includes a dielectric barrier between a gate and a blocking dielectric on a charge trap region of the charge trap structure. In various embodiments, material of the dielectric barrier of each of the charge trap structures may have a dielectric constant greater than that of aluminum oxide. Additional apparatus, systems, and methods are disclosed.
1. An apparatus comprising:
a semiconductor pillar operable to conduct a current, the semiconductor pillar extending vertically from a substrate;
a charge trap region separated from the semiconductor pillar by a tunnel region;
a dielectric blocking region adjacent to the charge trap region;
a first gate operable to control storage of charge in the charge storage region;
a second gate;
an isolation dielectric extending vertically between the first gate and the second gate and contacting the first gate and the second gate;
a dielectric barrier between the dielectric blocking region and the first gate, the dielectric barrier comprising material different from material of the dielectric blocking region, the dielectric barrier structured as a nanolaminate vertically along and contacting the dielectric blocking region, the first gate, the isolation dielectric, and the second gate, wherein the nanolaminate comprises at least three different material layers with the nanolaminate having a dielectric constant greater than that of aluminum oxide.
2. The apparatus of claim 1 , wherein the material of the dielectric barrier has a dielectric constant (κ) in a range of 12<κ<40.
3. The apparatus of claim 1 , wherein the material of the dielectric barrier has an electron affinity lower than that aluminum oxide.
4. The apparatus of claim 3 , wherein the material dielectric barrier has an electron affinity in a range of 1.5 eV<χ<2.5 eV.
5. The apparatus of claim 1 , wherein the material of the dielectric barrier includes one or more of hafnium oxide, zirconium oxide, or a mixture of hafnium oxide and/or zirconium oxide with one or more of aluminum oxide, silicon oxide, titanium oxide, gadolinium oxide, niobium oxide, or tantalum oxide.
6. The apparatus of claim 1 , wherein the charge trap region includes a dielectric silicon nitride.
7. The apparatus of claim 1 , wherein the gate includes conductive titanium nitride.
8. The apparatus of claim 7 , wherein the gate includes tungsten on and contacting the conductive titanium nitride.
9. A memory device comprising:
a string of memory cells including:
a vertical pillar of semiconductor material the vertical pillar extending vertically from a substrate; and
multiple charge storage devices arranged along the vertical pillar with an isolation dielectric between directly adjacent charge storage devices of the multiple charge storage devices, each charge storage device of the multiple charge storage devices including:
a charge trap region separated from the vertical pillar of the vertical string by a tunnel region;
a dielectric blocking region adjacent to the charge trap region;
a gate adjacent to the dielectric blocking region and operable to control storage of charge in the charge storage region; and
a dielectric barrier between the dielectric blocking region and the gate, material of the dielectric barrier being different from material of the dielectric blocking region, the dielectric barrier structured as a nanolaminate vertically along and contacting the dielectric blocking region and the gate, with the nanolaminate having multiple layers in which each layer of the nanolaminate has a dielectric constant greater than that of aluminum oxide, wherein the dielectric barrier of each charge storage device is part of a region that vertically extends continuously along and contacts the gate of each charge storage device and extends continuously along and contacts the isolation dielectrics between the charge storage devices arranged along the vertical pillar.
10. The memory device of claim 9 , wherein the material of the dielectric barrier includes hafnium oxide.
11. The memory device of claim 9 , wherein the material of the dielectric barrier includes zirconium oxide.
12. The memory device of claim 9 , wherein the material of the dielectric barrier includes a mixture of hafnium oxide with one or more of aluminum oxide, silicon oxide, titanium oxide, gadolinium oxide, niobium oxide, or tantalum oxide.
13. The memory device of claim 9 , wherein the material of the dielectric barrier includes a mixture of zirconium oxide with one or more of aluminum oxide, silicon oxide, titanium oxide, gadolinium oxide, niobium oxide, or tantalum oxide.
14. The memory device of claim 9 , wherein the dielectric barrier has a thickness in a range from about 15 angstroms to about 50 angstroms from the dielectric blocking region to the gate.
15. The memory device of claim 9 , wherein the tunnel region is a three region tunnel barrier.
16. The memory device of claim 15 , wherein the three region tunnel barrier is a region of dielectric oxide, a region of dielectric nitride disposed on the dielectric oxide, and another region of dielectric oxide disposed on the region of dielectric nitride.
17. The memory device of claim 9 , wherein the tunnel region is a two region tunnel barrier.
18. The memory device of claim 9 , wherein the tunnel region is a one region tunnel barrier.
19. The memory device of claim 9 , wherein the gate is a metal gate.
20. The memory device of claim 9 , wherein the pillar of semiconductor material comprises poly silicon.
21. A memory device comprising:
a string of memory cells including:
a vertical pillar of semiconductor material, the vertical pillar extending vertically from a substrate; and
multiple charge storage devices arranged along the vertical pillar with an isolation dielectric between directly adjacent charge storage devices of the multiple charge storage devices, each charge storage device of the multiple charge storage devices including:
a charge trap region separated from the vertical pillar of the vertical string by a tunnel region;
a dielectric blocking region adjacent to the charge trap region;
a gate adjacent to the dielectric blocking region and operable to control storage of charge in the charge storage region; and
a dielectric barrier between the dielectric blocking region and the gate, the dielectric barrier being different from the dielectric blocking region, the dielectric barrier structured as a nanolaminate vertically along and contacting the dielectric blocking region and the gate, with the nanolaminate having multiple layers in which each layer of the nanolaminate has a dielectric constant greater than that of aluminum oxide, the nanolaminate having an electron affinity lower than 2.8 eV, wherein the dielectric barrier of each charge storage device is part of a region that vertically extends continuously along and contacts the gate of each charge storage device and extends continuously along and contacts the isolation dielectrics between the charge storage devices arranged along the vertical pillar.
22. The memory device of claim 21 , wherein the material of the dielectric barrier has a dielectric constant (κ) in a range of 12<κ<40.
23. The memory device of claim 21 , wherein the material dielectric barrier has an electron affinity in a range of 1.5 eV<χ<2.5 eV.
24. The memory device of claim 21 , wherein the tunnel region includes a region of a first dielectric oxide, a region of dielectric nitride disposed on the dielectric oxide, and a region of a second dielectric oxide disposed on the region of dielectric nitride.