Apparatuses, multi-chip modules and capacitive chips

1. A capacitive chip comprising a plurality of capacitive units, the individual capacitive units comprising:

alternating electrode layers and dielectric layers in a capacitor stack; the capacitor stack extending across an undulating topography; the undulating topography comprising peaks and valleys with the peaks being elevationally offset relative to the valleys by a distance within a range of from about 30 microns to about 100 microns;

the capacitor stack comprising at least about 10 total layers;

the capacitive chip having capacitive density within a range of from about 1 μF/mm 2 to about 20 μF/mm 2 ; and

wherein the capacitive units on the capacitive chip together may have total capacitance within a range of from about 10 microfarads to about 200 microfarads under voltage within a range of from about 1 volt to about 5 volts.

2. A capacitive chip comprising a plurality of capacitive units, the individual capacitive units comprising:

alternating electrode layers and dielectric layers in a capacitor stack; the capacitor stack extending across an undulating topography; the undulating topography comprising peaks and valleys with the peaks being elevationally offset relative to the valleys by a distance within a range of from about 30 microns to about 100 microns;

the capacitor stack comprising at least about 10 total layers;

the capacitive chip having capacitive density within a range of from about 1 μF/mm 2 to about 20 μF/mm 2 ; and

comprising at least about 1 capacitive unit per square millimeter.

3. A capacitive chip comprising a plurality of capacitive units, the individual capacitive units comprising:

alternating electrode layers and dielectric layers in a capacitor stack; the capacitor stack extending across an undulating topography; the undulating topography comprising peaks and valleys with the peaks being elevationally offset relative to the valleys by a distance within a range of from about 30 microns to about 100 microns;

the capacitor stack comprising at least about 10 total layers;

the capacitive chip having capacitive density within a range of from about 1 μF/mm 2 to about 20 μF/mm 2 ; and

comprising at least about 4 capacitive units per square millimeter.

4. A capacitive chip comprising a plurality of capacitive units, the individual capacitive units comprising:

alternating electrode layers and dielectric layers in a capacitor stack; the capacitor stack extending across an undulating topography; the undulating topography comprising peaks and valleys with the peaks being elevationally offset relative to the valleys by a distance within a range of from about 30 microns to about 100 microns;

the capacitor stack comprising at least about 10 total layers;

the capacitive chip having capacitive density within a range of from about 1 μF/mm 2 to about 20 μF/mm 2 ; and

wherein all of the capacitive units are substantially identical to one another in capacitance.

5. A capacitive chip comprising a plurality of capacitive units, the individual capacitive units comprising:

alternating electrode layers and dielectric layers in a capacitor stack; the capacitor stack extending across an undulating topography; the undulating topography comprising peaks and valleys with the peaks being elevationally offset relative to the valleys by a distance within a range of from about 30 microns to about 100 microns;

the capacitor stack comprising at least about 10 total layers;

the capacitive chip having capacitive density within a range of from about 1 μF/mm 2 to about 20 μF/mm 2 ; and

wherein at least one of the capacitive units has a substantially different capacitance than another of the capacitive units.

6. A capacitive chip comprising a plurality of capacitive units, the individual capacitive units comprising:

alternating electrode layers and dielectric layers in a capacitor stack; the capacitor stack extending across an undulating topography; the undulating topography comprising peaks and valleys with the peaks being elevationally offset relative to the valleys by a distance within a range of from about 30 microns to about 100 microns;

the capacitive chip having capacitive density within a range of from about 1 μF/mm 2 to about 20 μF/mm 2 ; and

wherein the capacitor stack comprises at least about 30 total layers.

7. The capacitive chip of claim 6 wherein the capacitor stack comprises at least about 50 total layers.

8. A capacitive chip comprising a plurality of capacitive units, the individual capacitive units comprising:

alternating electrode layers and dielectric layers in a capacitor stack; the capacitor stack extending across an undulating topography; the undulating topography comprising peaks and valleys with the peaks being elevationally offset relative to the valleys by a distance within a range of from about 30 microns to about 100 microns;

the capacitive chip having capacitive density within a range of from about 1 μF/mm 2 to about 20 μF/mm 2 ; and

wherein the capacitor stack comprises from at least about 10 total layers to at least about 100 total layers.

9. A capacitive chip comprising a plurality of capacitive units, the individual capacitive units comprising:

alternating electrode layers and dielectric layers in a capacitor stack; the capacitor stack extending across an undulating topography; the undulating topography comprising peaks and valleys with the peaks being elevationally offset relative to the valleys by a distance within a range of from about 30 microns to about 100 microns;

the capacitor stack comprising at least about 10 total layers;

the capacitive chip having capacitive density within a range of from about 1 μF/mm 2 to about 20 μF/mm 2 ; and

wherein the electrode layers are all a same composition as one another.

10. A capacitive chip comprising a plurality of capacitive units, the individual capacitive units comprising:

alternating electrode layers and dielectric layers in a capacitor stack; the capacitor stack extending across an undulating topography; the undulating topography comprising peaks and valleys with the peaks being elevationally offset relative to the valleys by a distance within a range of from about 30 microns to about 100 microns;

the capacitor stack comprising at least about 10 total layers;

the capacitive chip having capacitive density within a range of from about 1 μF/mm 2 to about 20 μF/mm 2 ; and

wherein the dielectric layers are all a same composition as one another.

11. A capacitive chip comprising a plurality of capacitive units, the individual capacitive units comprising:

alternating electrode layers and dielectric layers in a capacitor stack; the capacitor stack extending across an undulating topography; the undulating topography comprising peaks and valleys with the peaks being elevationally offset relative to the valleys by a distance within a range of from about 30 microns to about 100 microns;

the capacitor stack comprising at least about 10 total layers;

the capacitive chip having capacitive density within a range of from about 1 μF/mm 2 to about 20 μF/mm 2 ; and

wherein the undulating surface extends into a semiconductor substrate.

12. A capacitive chip comprising a plurality of capacitive units, the individual capacitive units comprising:

alternating electrode layers and dielectric layers in a capacitor stack; the capacitor stack extending across an undulating topography; the undulating topography comprising peaks and valleys with the peaks being elevationally offset relative to the valleys by a distance within a range of from about 30 microns to about 100 microns;

the capacitor stack comprising at least about 10 total layers;

the capacitive chip having capacitive density within a range of from about 1 μF/mm 2 to about 20 μF/mm 2 ; and

wherein the undulating surface is along glass.