Semiconductor package and fabrication method thereof

1. A semiconductor package, comprising:

a first logic die;

a second logic die located laterally adjacent to the first logic die, a first active face of the first logic die and a second active face of the second logic die facing a same direction;

a bridge memory die coupled to both the first logic die and the second logic die on the first active face and the second active face;

a redistribution layer (RDL) structure directly, electrically coupled to the first logic die, the second logic die, and the bridge memory die, wherein the bridge memory die is directly coupled to metal layers of the RDL structure by a plurality of through substrate vias extending from proximate the first active face and the second active face, through the bridge memory die, to the RDL structure and the first logic die and the second logic die are directly coupled to the metal layers of the RDL structure by connecting elements extending from the first active face and the connecting elements extending from the second active face, laterally adjacent to the bridge memory die, to the RDL structure, the bridge memory die being interposed between at least a portion of the first logic die and the RDL structure and between at least a portion of the second logic die and the RDL structure; and

a molding compound at least partially encapsulating the first logic die, the second logic die, and the bridge memory die wherein the molding compound comprising at least a through mold via directly connected to the metal of the RDL structure.

2. The semiconductor package of claim 1 , wherein the first active face of the first logic die and the second active face of the second logic die are coplanar.

3. The semiconductor package of claim 1 , wherein the bridge memory die is electrically coupled to the first logic die and the second logic die in a flip-chip configuration, such that an active face of the bridge memory die faces the first active face and the second active face.

4. The semiconductor package of claim 1 , wherein the bridge memory die is a dual-port RAM.

5. The semiconductor package of claim 1 , wherein each of the first logic die and the second logic die comprises central processing units, graphics processing units, or application processors.

6. The semiconductor package of claim 1 , wherein the bridge memory die enables inter-processor communication between the first logic die and the second logic die.

7. The semiconductor package of claim 1 , wherein the at least one through mold via is located laterally adjacent to the bridge memory die.

8. The semiconductor package of claim 1 , further comprising a plurality of solder bumps or solder balls mounted on a side of the RDL structure opposite the bridge memory die.

9. The semiconductor package of claim 1 , wherein a first inactive face of the first logic die and a second inactive face of the second logic die are exposed and coplanar with a face of the molding compound on a side of the semiconductor package opposite the RDL structure.

10. A method of making a semiconductor package, comprising:

coupling a bridge memory die to first logic die and a second logic die, the bridge memory die located on a first active face of the first logic die and a second active face of the second logic die, the first active face facing a same direction as the second active face;

at least partially encapsulating the first logic die, the second logic die, and the bridge memory die in a molding compound; and

directly, electrically coupling a redistribution layer (RDL) structure to the first logic die, the second logic die, and the bridge memory die, wherein the bridge memory die is directly coupled to metal layers of the RDL structure by a plurality of through substrate vias extending from proximate the first active face and the second active face, through the bridge memory die, to the RDL structure and the first logic die and the second logic die are directly coupled to said metal layers of the RDL structure by connecting elements extending from the first active face and said connecting elements extending from the second active face, laterally adjacent to the bridge memory die, to the RDL structure, the bridge memory die being interposed between at least a portion of the first logic die and the RDL structure and between at least a portion of the second logic die wherein the molding compound comprising at least a through mold via directly connected to metal layers of the RDL structure and the RDL structure.

11. The method of claim 10 , wherein coupling the bridge memory die to the first logic die and the second logic die comprises coupling the bridge memory die to the first logic die and the second logic die, the first active face of the first logic die and the second active face of the second logic die being coplanar.

12. The method of claim 10 , wherein coupling the bridge memory die to the first logic die and the second logic die comprises coupling the bridge memory die to the first logic die and the second logic die in a flip-chip configuration, such that an active surface of the bridge memory die faces the first active face and the second active face.

13. The method of claim 10 , further comprising placing the at least one through mold via on the respective one of the first logic die and the second logic die before coupling the bridge memory die to the first logic die and the second logic die.

14. The method of claim 10 , further comprising mounting a plurality of solder bumps or solder balls on a side of the RDL structure opposite the bridge memory die.

15. The method of claim 10 , wherein at least partially encapsulating the first logic die, the second logic die, and the bridge memory die in the molding compound comprises leaving a first inactive surface of the first logic die and a second inactive surface of the second logic die exposed and coplanar with a surface of the molding compound on a side of the semiconductor package opposite the RDL structure.

16. The method of claim 10 , further comprising temporarily securing the first logic die and the second logic die to a carrier before coupling the bridge memory die to the first logic die and the second logic die.

17. The method of claim 16 , further comprising removing the carrier from the first logic die and the second logic die after at least partially encapsulating the first logic die, the second logic die, and the bridge memory die in the molding compound and after coupling the RDL structure to the first logic die, the second logic die, and the bridge memory die.

18. The method of claim 10 , further comprising singulating the semiconductor package, including the first logic die, the second logic die, the bridge memory die, the RDL structure, and the molding compound, from at least one other similarly configured semiconductor package.