Systems and methods for refreshing a memory bank while accessing another memory bank using a shared address path

1. A system comprising:

a plurality of memory banks configured to store data, wherein the plurality of memory banks comprises a first set of memory banks and a second set of memory banks;

an address path coupled to the plurality of memory banks, wherein the address path is configured to provide a row address to the plurality of memory banks; and

a command address input circuit coupled to the address path, wherein the command address input circuit is configured to refresh the first set of memory banks via the address path and, when the command address input circuit refreshes the first set of memory banks, activate a row of the second set of memory banks to store the data or read the data from the row of the second set of memory banks via the address path, wherein the command address input circuit comprises:

a first counter configured to store and increment a first row address of the first set of memory banks to be refreshed; and

a second counter configured to store and increment a second row address of the second set of memory banks to be refreshed.

2. The system of claim 1 , wherein the command address input circuit is configured to refresh the second set of memory banks via the address path and, when the command address input circuit refreshes the second set of memory banks, activate a second row of the first set of memory banks to store the data or read the data from the row of the first set of memory banks via the address path.

3. The system of claim 1 , wherein the command address input circuit is configured to refresh the plurality of memory banks of the semiconductor device by outputting at least the first row address of the first set of memory banks to be refreshed or the second row address of the second set of memory banks to be refreshed to the address path.

4. The system of claim 1 , wherein the command address input circuit is configured to refresh the first set of memory banks of the semiconductor device by outputting at least the first row address of the first set of memory banks to be refreshed to the address path.

5. The system of claim 1 , wherein the command address input circuit is configured to refresh the second set of memory banks of the semiconductor device by outputting at least the second row address of the second set of memory banks to be refreshed to the address path.

6. A system comprising:

a register configured to store a row address;

a plurality of memory banks configured to store data, wherein the plurality of memory banks comprises a first set of memory banks and a second set of memory banks; and

a plurality of bank control blocks coupled to the plurality of memory banks, wherein the plurality of bank control blocks comprises:

a first set of bank control blocks configured to refresh the first set of memory banks by:

capturing the row address from the register;

refreshing a first row of the first set of memory banks, wherein the first row is associated with the row address that was captured from the register;

incrementing the row address that was captured from the register; and

refreshing a second row of the first set of memory banks, wherein the second row is associated with the row address that was captured from the register and incremented; and

a second set of bank control blocks configured to activate a third row of the second set of memory banks, and, at the same time, the first set of bank control blocks refreshes the first row of the first set of memory banks, refreshes the second row of the first set of memory banks, or a combination thereof.

7. The system of claim 6 , wherein:

the second set of bank control blocks is configured to refresh the second set of memory banks by:

capturing a second row address from the register;

refreshing a fourth row of the second set of memory banks, wherein the fourth row is associated with the second row address that was captured from the register;

incrementing the second row address that was captured from the register to produce an incremented second row address; and

refreshing a fifth row of the second set of memory banks, wherein the fifth row is associated with the incremented second row address; and

the first set of bank control blocks is configured to activate a sixth row of the first set of memory banks, and, at the same time, the second set of bank control blocks refreshes the fourth row of the second set of memory banks, refreshes the fifth row of the second set of memory banks, or a combination thereof.

8. A row address output circuit comprising:

a first counter configured to store and increment a first row address of a first set of memory banks of a semiconductor device to be refreshed;

a second counter configured to store and increment a second row address of the second set of memory banks of the semiconductor device to be refreshed; and

a multiplexer configured to:

receive, as inputs, the first row address from the first counter, the second row address from the second counter, a third row address associated with a first row of the first set of memory banks or a second row of the second set of memory banks to be activated, and a selection signal;

output the first row address when the selection signal is associated with refreshing the plurality of memory banks or refreshing the first set of memory banks;

output the second row address when the selection signal is associated with refreshing the plurality of memory banks or refreshing the second set of memory banks; and

output the third row address when the selection signal is associated with activating the first row of the first set of memory banks or the second row of the second set of memory banks, wherein the first set of memory banks is configured to be refreshed during activation of the second row of the second set of memory banks, wherein the second set of memory banks is configured to be refreshed during activation of the first row of the first set of memory banks.

9. The row address output circuit of claim 8 , wherein the first counter is configured to increment the first row address and the second counter is configured to increment the second row address when the selection signal is associated with refreshing the plurality of memory banks and the first row address is the same as the second row address.

10. The row address output circuit of claim 8 , wherein the second counter is configured to increment the second row address when the selection signal is associated with refreshing the plurality of memory banks and the first row address is greater than the second row address.

11. The row address output circuit of claim 8 , wherein the first counter is configured to increment the first row address when the selection signal is associated with refreshing the plurality of memory banks and the first row address is less than the second row address.

12. The row address output circuit of claim 8 , wherein the first counter is configured to increment the first row address when the selection signal is associated with refreshing the first set of memory banks and the first row address is less than or equal to the second row address.

13. The row address output circuit of claim 8 , wherein the second counter is configured to increment the second row address when the selection signal is associated with refreshing the second set of memory banks and the second row address is less than or equal to the second row address.

14. A method comprising:

receiving a command at a semiconductor device;

when the command is configured to refresh a plurality of memory banks of the semiconductor device, outputting a first row address of a first set of memory banks of the plurality of memory banks or a second row address of a second set of memory banks of the plurality of memory banks to be refreshed, wherein the first row address is stored in a first counter of the semiconductor device and the second row address is stored in a second counter of the semiconductor device;

when the command is configured to separately refresh the first set of memory banks, outputting the first row address stored in the first counter;

when the command is configured to separately refresh the second set of memory banks, outputting the second row address stored in the second counter;

when the command is configured to activate a first row of the first set of memory banks, receiving and outputting a third row address associated with the first row, wherein the second set of memory banks is configured to be refreshed during activation of the first row of the first set of memory banks; and

when the command is configured to activate a second row of the second set of memory banks, receiving and outputting a fourth row address associated with the second row, wherein the first set of memory banks is configured to be refreshed during activation of the second row of the second set of memory banks.

15. The method of claim 14 , wherein, when the command is configured to separately refresh the first set of memory banks, the command is configured to refresh a plurality of rows of the first set of memory banks.

16. The method of claim 14 , comprising, when the command is configured to refresh the plurality of memory banks and the first row address is the same as the second row address, incrementing the first row address stored in the first counter and the second row address stored in the second counter.

17. The method of claim 14 , when the command is configured to refresh the plurality of memory banks and the first row address is greater than the second row address, incrementing the second row address stored in the second counter and not incrementing the first row address stored in the first counter.

18. The method of claim 14 , when the command is configured to refresh the plurality of memory banks and the first row address is less than the second row address, incrementing the first row address stored in the first counter and not incrementing the second row address stored in the second counter.

19. The method of claim 14 , comprising, when the command is configured to separately refresh the first set of memory banks and the first row address is less than or equal to the second row address, incrementing the first row address stored in the first counter.

20. The method of claim 14 , comprising, when the command is configured to separately refresh the second set of memory banks and the second row address is less than or equal to the first row address, incrementing the second row address stored in the second counter.