Clock and data recovery having shared clock generator
This disclosure provides a clock recovery circuit for a multi-lane communication system. Local clocks are recovered from the input signals using respective local CDR circuits, and associated CDR error signals are aggregated or otherwise combined. A global recovered clock for shared use by the local CDR circuits is generated at a controllable oscillation frequency as a function of a combination of the error signals from the plurality of receivers. A voltage- or current-controlled delay line can also be used to phase adjust the global recovered clock to mitigate band-limited, lane-correlated, high frequency jitter.
1. An apparatus, comprising:
receivers, each to receive a respective data signal arriving via a respective signaling lane, each data signal transmitted in response to a common clock source and carrying a respective embedded clock, wherein each of the receivers is to generate a respective local error signal representing a timing error between the respective embedded clock and a timing derived from a global clock;
a controllable oscillator to generate an oscillation signal in response to a first control signal; and
a delay locked loop to receive the oscillation signal and to generate an output, the global clock dependent on the output, the delay locked loop to impart a delay in response to a second control signal;
wherein the first control signal and the second control signal are each to be generated as a function of the local error signals generated by the receivers.
2. The apparatus of claim 1 , wherein the second control signal is to be generated so as to cause the imparted delay to be responsive to phase differences represented by the local error signals at a first bandwidth, and wherein the first control signal is to be generated so as to cause the oscillation signal to have a frequency responsive to phase differences represented by the local error signals that are not offset by a variation in the imparted delay, at a second loop bandwidth.
3. The apparatus of claim 1 , wherein the apparatus is embodied in an integrated circuit, and wherein each of the respective data signals is to be generated externally from the integrated circuit.
4. The apparatus of claim 3 , wherein said apparatus is a first one of a memory controller and a memory device, and wherein each of the respective data signals is to be generated externally by a second one of the memory controller and the memory device.
5. The apparatus of claim 1 , wherein each of the receivers comprises a local clock recovery circuit to generate the respective local error signal and a respective local recovered clock, wherein each respective local error signal represents the timing error between the respective embedded clock and the respective local clock, and wherein each respective local clock is dependent on the timing provided by the global clock.
6. The apparatus of claim 1 , wherein the apparatus further comprises an accumulator to receive the respective local error signals and to generate an output, and wherein the first control signal is dependent on the output of the accumulator.
7. The apparatus of claim 6 , wherein the apparatus further comprises a delta-sigma modulator to receive the output of the accumulator, and wherein the first control signal is dependent on an output of the delta-sigma modulator.
8. The apparatus of claim 1 , wherein the apparatus further comprises a summing junction to receive the respective local error signals and to generate an output, and a low pass filter, wherein the low pass filter is dependent on the output of the summing junction, and wherein the second control signal is dependent on an output of the low pass filter.
9. The apparatus of claim 1 , wherein the first control signal and the second control signal each provide a variable-magnitude voltage or current, wherein the controllable oscillator is a voltage-controlled or current-controlled oscillator that is to be driven in response to the first control signal, and wherein the delay locked loop comprises a voltage-controlled or current-controlled delay line that is to be driven in response to the second control signal.
10. An integrated circuit (IC), comprising:
receivers, each to receive a respective data signal arriving via a respective signaling lane, each data signal being generated externally from said IC, being transmitted in response to a common clock source and carrying a respective embedded clock, wherein each of the receivers is to generate a respective local error signal representing a timing error between the respective embedded clock and a timing derived from a global clock;
a controllable oscillator to generate an oscillation signal in response to a first control signal; and
a delay locked loop to receive the oscillation signal and to generate an output, the global clock dependent on the output, the delay locked loop to impart a delay in response to a second control signal;
wherein the first control signal and the second control signal are each to be generated as a function of the local error signals generated by the receivers.
11. The IC of claim 10 , wherein the second control signal is to be generated so as to cause the imparted delay to be responsive to phase differences represented by the local error signals at a first bandwidth, and wherein the first control signal is to be generated so as to cause the oscillation signal to have a frequency responsive to phase differences represented by the local error signals that are not offset by a variation in the imparted delay, at a second loop bandwidth.
12. The IC of claim 10 , wherein said IC comprises a first one of a memory controller and a memory device, and wherein each of the respective data signals is to be generated externally by a second one of the memory controller and the memory device.
13. The IC of claim 10 , wherein each of the receivers comprises a local clock recovery circuit to generate the respective local error signal and a respective local recovered clock, wherein each respective local error signal represents the timing error between the respective embedded clock and the respective local clock, and wherein each respective local clock is dependent on the timing provided by the global clock.
14. The IC of claim 10 , further comprising an accumulator to receive the respective local error signals and to generate an output, wherein the first control signal is dependent on the output of the accumulator.
15. The IC of claim 14 , further comprising a delta-sigma modulator to receive the output of the accumulator, wherein the first control signal is dependent on an output of the delta-sigma modulator.
16. The IC of claim 10 , further comprising a summing junction to receive the respective local error signals and to generate an output and a low pass filter, wherein the low pass filter is dependent on the output of the summing junction, and wherein the second control signal is dependent on an output of the low pass filter.
17. The IC of claim 10 , wherein the first control signal and the second control signal each provide a variable-magnitude voltage or current, wherein the controllable oscillator is a voltage-controlled or current-controlled oscillator that is to be driven in response to the first control signal, and wherein the delay locked loop comprises a voltage-controlled or current-controlled delay line that is to be driven in response to the second control signal.
18. A method, comprising:
via receivers, receiving respective data signals arriving via respective signaling lanes, each data signal transmitted in response to a common clock source and carrying a respective embedded clock, and generating respective local error signals representing a timing error between the respective embedded clocks and a timing derived from a global clock;
controlling an oscillator to generate an oscillation signal in response to a first control signal; and
using a delay locked loop to receive the oscillation signal, to impart a delay in response to a second control signal, and to generate an output;
wherein the global clock is dependent on the output; and
wherein the method further comprises generating the first control signal and the second control signal, each as a function of the local error signals generated by the receivers.
19. The method of claim 18 , wherein generating the second control signal is performed in a manner responsive to phase differences represented by the local error signals at a first bandwidth, and wherein generating the first control signal is performed so as to cause the oscillation signal to have a frequency responsive to phase differences represented by the local error signals that are not offset by a variation in the imparted delay, at a second loop bandwidth.
20. The method of claim 18 , wherein the method further comprises using a local clock recovery circuit for each of the receivers to generate the respective local error signals and a respective local recovered clock, wherein each respective local error signal represents the timing error timing error between the respective embedded clock and the respective local clock, and wherein each respective local clock is dependent on the timing provided by the global clock.