Method to form strained channel in thin box SOI structures by elastic strain relaxation of the substrate
Methods and structures for forming strained-channel FETs are described. A strain-inducing layer may be formed under stress in a silicon-on-insulator substrate below the insulator. Stress-relief cuts may be formed in the strain-inducing layer to relieve stress in the strain-inducing layer. The relief of stress can impart strain to an adjacent semiconductor layer. Strained-channel, fully-depleted SOI FETs and strained-channel finFETs may be formed from the adjacent semiconductor layer. The amount and type of strain may be controlled by etch depths and geometries of the stress-relief cuts and choice of materials for the strain-inducing layer.
1. A method, comprising:
forming a strain-inducing layer on a substrate;
forming a semiconductor layer having a first surface on the strain-inducing layer and a second surface opposite the first surface, the semiconductor layer including a source region, a drain region, and a channel region of a semiconductor device; and
forming at least one stress-relief trench that extends through the semiconductor layer and into the strain-inducing layer, the trench abuts side surfaces of the source region, the drain region, and the channel region, which side surfaces extend between the first and second surfaces of the semiconductor layer, and the trench imparts strain to the channel region.
2. The method of claim 1 wherein forming the semiconductor layer includes forming a semiconductor fin including the source region, the drain region, and the channel region.
3. The method of claim 1 wherein the strain-inducing layer comprises a first semiconductor material, and the substrate comprises a second semiconductor material that is different from the first semiconductor material.
4. The method of claim 1 , further comprising forming an insulating layer between the strain-inducing layer and the source region, the drain region, and the channel region of the semiconductor layer.
5. The method of claim 1 wherein forming the at least one stress-relief trench includes:
forming a first plurality of trenches extending in a first lateral direction; and
forming a second plurality of trenches extending in a second lateral direction that is transverse to the first lateral direction.
6. The method of claim 5 wherein forming the first plurality of trenches includes forming the first plurality of trenches through the strain-inducing layer and at least partially into the substrate.
7. A method, comprising:
forming a strain-inducing layer on a silicon-on-insulator (SOI) substrate, the strain-inducing layer extending over an area of the substrate;
forming an insulating layer on the strain-inducing layer;
forming a semiconductor layer extending over the area of the substrate, the semiconductor layer including a source region, a channel region, and a drain region, the insulating layer being between the strain-inducing layer and the source region, the channel region, and the drain region of the semiconductor layer
forming stress-relief trenches in the strain-inducing layer to relieve stress in the strain-inducing layer and impart strain to at least one active area for at least one field effect transistor (FET) formed in the semiconductor layer.
8. The method of claim 7 , further comprising:
forming a gate structure in the at least one active area.
9. The method of claim 7 wherein the source, channel, and drain regions are formed in the semiconductor layer, wherein the semiconductor layer is ultrathin and is disposed on an ultrathin buried oxide layer.
10. The method of claim 9 further comprising forming at least one epitaxial region on the drain and source regions that adds strain to the channel region in addition to strain induced in the channel region by the strain-inducing layer.
11. The method of claim 9 , further comprising forming bias circuitry for applying a bias voltage to the substrate as a back gate or body bias.
12. The method of claim 7 , further comprising:
forming at least one semiconductor fin in the semiconductor layer;
forming a gate structure over the at least one fin; and
forming the source, drain, and channel regions in the semiconductor fin.
13. The method of claim 7 wherein the strain-inducing layer comprises at least one of SiGe or SiC and the source, drain, and channel regions are formed of Si.
14. The method of claim 7 wherein forming the stress-relief trenches comprises:
forming a first plurality of trenches extending in a first lateral direction; and
forming a second plurality of trenches extending in a second lateral direction that is different from the first lateral direction.
15. The method of claim 14 , further comprising filling the first plurality of trenches and the second plurality of trenches with an insulating material.
16. The method of claim 14 wherein forming the first plurality of trenches includes etching the first plurality of trenches through the strain-inducing layer.
17. The method of claim 7 , further comprising:
forming the stress-relief trenches to define a first active area of the at least one active area, the first active area having a width W and a length S a ; and
forming source, drain, and channel regions in the first active area.
18. A method, comprising:
forming a strain-inducing layer on a silicon-on-insulator (SOI) substrate, the strain-inducing layer extending over an area of the substrate;
forming a semiconductor layer extending over the area of the substrate and adjacent the strain-inducing layer;
forming stress-relief trenches in the strain-inducing layer to relieve stress in the strain-inducing layer and impart strain to at least one active area for at least one field effect transistor (FET) formed in the semiconductor layer;
forming the stress-relief trenches to define a first active area of the at least one active area, the first active area having a width W and a length S a ; and
forming source, drain, and channel regions in the first active area,
wherein the length S a is formed to be greater than four times a total thickness of the strain-inducing layer, the semiconductor layer, and an insulating layer between the strain-inducing layer and the semiconductor layer.
19. A method, comprising:
forming at least one strained-channel field effect transistor (FET) on a substrate, the forming including:
forming a strain-inducing layer on an area of the substrate;
forming an insulating layer on the strain-inducing layer;
forming a semiconductor layer extending on the area of the substrate, the semiconductor layer including a source region, a channel region, and a drain region, the insulating layer being between the strain-inducing layer and the source region, the channel region, and the drain region of the semiconductor layer; and
forming a plurality of stress-relief trenches in the strain-inducing layer, the stress-relief trenches abutting side surfaces of the source region, the drain region, and the channel region of the semiconductor layer.
20. The method of claim 19 , further comprising relieving stress in the strain-inducing layer and imparting strain to at least the channel region of the semiconductor layer.
21. The method of claim 20 , further comprising:
forming a gate structure on the channel region.
22. The method of claim 19 , further comprising:
forming at least one semiconductor fin in the semiconductor layer;
forming a gate structure over the at least one fin; and
forming the source, drain, and channel regions in the semiconductor fin.
23. The method of claim 19 wherein forming the stress-relief trenches includes:
forming a first plurality of isolating trenches extending in a first direction; and
forming a second plurality of isolating trenches extending in a second direction that is different from the first direction.
24. The method of claim 18 , further comprising:
forming an insulating layer between the strain-inducing layer and the semiconductor layer.