IP Library Granted Patent US 10,211,313
Granted Patent B2
US 10,211,313 · App. 15/678,125 · Granted Feb 19, 2019

Semiconductor device and method for fabricating the same

Inventors: Shih-Hung Tsai (Tainan, TW); Po-Kuang Hsieh (Kaohsiung, TW); Yu-Ting Tseng (Tainan, TW); Cheng-Ping Kuo (Pingtung County, TW); Kuan-Hao Tseng (Kaohsiung, TW)
Assignee: UNITED MICROELECTRONICS CORP.
H01L29/516H01L21/02194H01L21/02356H01L21/28255H01L29/408H01L29/66545H01L29/66795H01L29/785
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Quick Facts
Patent No.
US 10,211,313
App. No.
15/678,125
Granted
Feb 19, 2019
Kind
B2
Abstract

A method for fabricating semiconductor device includes the steps of: forming a gate structure on a substrate; forming an interlayer dielectric (ILD) layer around the gate structure; removing the gate structure to form a first recess; forming ferroelectric (FE) layer in the first recess; forming a compressive layer on the FE layer; performing a thermal treatment process; removing the compressive layer; and forming a work function metal layer in the recess.

Claims (26)

1. A method for fabricating semiconductor device, comprising:

forming a gate structure on a substrate;

forming an interlayer dielectric (ILD) layer around the gate structure;

removing the gate structure to form a first recess;

forming ferroelectric (FE) layer in the first recess;

forming a compressive layer on the FE layer;

performing a thermal treatment process directly on the compressive layer;

removing the compressive layer;

forming a work function metal layer in the recess;

forming a low resistance metal layer on the work function metal layer;

performing a planarizing process to form a metal gate;

removing part of the metal gate to form a second recess; and

forming a polysilicon layer in the second recess and on the ILD layer.

2. The method of claim 1 , further comprising:

forming a fin-shaped structure on the substrate; and

forming the gate structure on the fin-shaped structure, wherein the fin-shaped structure comprises silicon germanium.

3. The method of claim 1 , further comprising:

removing part of the polysilicon layer to form a third recess; and

forming a hard mask on the polysilicon layer.

4. The method of claim 1 , wherein the polysilicon layer comprises a n-type polysilicon layer.

5. The method of claim 1 , wherein the polysilicon layer is U-shaped.

6. The method of claim 1 , further comprising:

forming a high-k dielectric layer in the first recess; and

forming a bottom barrier metal (BBM) layer on the high-k dielectric layer before forming the FE layer.

7. The method of claim 1 , wherein the FE layer comprises HfZrO 2 .

8. The method of claim 1 , wherein the compressive layer comprises a compressive TiN layer.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 8, 2017
From: TSAI, SHIH-HUNG; HSIEH, PO-KUANG; TSENG, YU-TING; KUO, CHENG-PING; TSENG, KUAN-HAO
To: UNITED MICROELECTRONICS CORP.
Reel/Frame 043528/0270 →
Priority Claims (1)
TW 106123732 A · Jul 17, 2017 · national
Continuity (1)
Related Publication 20190019875A1 · Jan 17, 2019
Cited By (1)
US 12,211,836