IP Library Granted Patent US 10,103,034
Granted Patent B2
US 10,103,034 · App. 15/678,134 · Granted Oct 16, 2018

Method of planarizing substrate surface

Inventors: Li-Chieh Hsu (Taichung, TW); Fu-Shou Tsai (Keelung, TW); Yu-Ting Li (Chiayi, TW); Yi-Liang Liu (Tainan, TW); Kun-Ju Li (Tainan, TW)
Assignee: UNITED MICROELECTRONICS CORP.
H01L21/31053H01L29/0653H01L29/7851
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Quick Facts
Patent No.
US 10,103,034
App. No.
15/678,134
Granted
Oct 16, 2018
Kind
B2
Abstract

A method of planarizing a substrate surface is disclosed. A substrate having a major surface of a material layer is provided. The major surface of the material layer comprises a first region with relatively low removal rate and a second region of relatively high removal rate. A photoresist pattern is formed on the material layer. The photoresist pattern masks the second region, while exposes at least a portion of the first region. At least a portion of the material layer not covered by the photoresist pattern is etched away. A polish stop layer is deposited on the material layer. A cap layer is deposited on the polish stop layer. A chemical mechanical polishing (CMP) process is performed to polish the cap layer.

Claims (14)

1. A method of planarizing a substrate surface, comprising:

providing a substrate having a major surface of a material layer, wherein the major surface of the material layer comprises a first region with relatively low removal rate and a second region of relatively high removal rate;

depositing a polish stop layer on the major surface of the material layer;

forming a photoresist pattern on the polish stop layer, wherein the photoresist pattern masks the second region of relatively high removal rate, while exposes at least a portion of the first region with relatively low removal rate;

etching away at least a portion of the polish stop layer not covered by the photoresist pattern; and

removing the photoresist pattern.

2. The method according to claim 1 , wherein after removing the photoresist pattern, the method further comprises:

depositing a cap layer on the polish stop layer and on the material layer; and

performing a chemical mechanical polishing (CMP) process to polish the cap layer.

3. The method according to claim 2 , wherein the material layer comprises amorphous silicon.

4. The method according to claim 2 , wherein the CMP process stops on the polish stop layer.

5. The method according to claim 4 , wherein the polish stop layer comprises silicon nitride, and wherein the cap layer comprises silicon oxide or amorphous silicon.

6. The method according to claim 2 , wherein after performing the CMP process to polish the cap layer and the material layer, the method further comprises:

performing a dry etching process to etch the polishing stop layer and the material layer.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 26, 2021
From: UNITED MICROELECTRONICS CORPORATION
To: MARLIN SEMICONDUCTOR LIMITED
Reel/Frame 056991/0292 →
Continuity (2)
Division 15201628 · Jul 5, 2016
Related Publication 20180012772A1 · Jan 11, 2018