IP Library Granted Patent US 10,326,044
Granted Patent B2
US 10,326,044 · App. 15/680,461 · Granted Jun 18, 2019

Method and apparatus for processing semiconductor device structures

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 10,326,044
App. No.
15/680,461
Granted
Jun 18, 2019
Kind
B2
Abstract

A method of processing a device wafer comprising applying a sacrificial material to a surface of a carrier wafer, adhering a surface of the device wafer to an opposing surface of the carrier wafer, planarizing an exposed surface of the sacrificial material by removing only a portion of a thickness thereof, and planarizing an opposing surface of the device wafer. A wafer assembly is also disclosed.

Claims (30)

1. A method of processing a device wafer, comprising:

planarizing an exposed surface of a carrier wafer bonded to a device wafer without removing material from the carrier wafer; and

reducing a thickness of the device wafer from an exposed surface thereof and planarizing an exposed surface of the device wafer after the thickness has been reduced.

2. The method of claim 1 , further comprising:

before bonding the device wafer to the carrier wafer, applying a sacrificial material to a surface of the carrier wafer; and further comprising bonding the device wafer to a surface of the carrier wafer uncoated with the sacrificial material.

3. The method of claim 2 , wherein applying a sacrificial material to a surface of the carrier wafer comprises applying at least one of a photoresist, a spin-on dielectric (SOD) material, an anti-reflective coating (ARC) material, a silicon oxide material or a silicon nitride material.

4. The method of claim 2 , further comprising planarizing the exposed surface of the carrier wafer by grinding away a portion of a thickness of the sacrificial material with a tool; and

reducing a thickness of the device wafer and planarizing the device wafer by grinding using the same tool.

5. The method of claim 4 , further comprising applying the sacrificial material to a thickness of between about 15 μm and about 30 μm, and grinding away a portion of a thickness of the sacrificial material comprises removing about 12 μm to about 15 μm of the thickness.

6. The method of claim 4 , further comprising:

removing any remaining portion of the sacrificial material from the carrier wafer; and

then removing the carrier wafer from the device wafer.

7. The method of claim 4 , further comprising removing the carrier wafer from the planarized device wafer while a portion of the sacrificial material remains on the carrier wafer.

8. A method of processing a device wafer, the method comprising:

before bonding a surface of a device wafer to a carrier wafer, applying a sacrificial material to a surface of a carrier wafer;

bonding the surface of the device wafer to an opposing surface of the carrier wafer;

planarizing an exposed surface of the sacrificial material by removing only a portion of a thickness thereof; and

planarizing an opposing surface of the device wafer.

9. The method of claim 8 , wherein applying a sacrificial material to a surface of a carrier wafer comprises applying at least one of a photoresist, a spin-on dielectric (SOD) material, an anti-reflective coating (ARC) material, a silicon oxide material or a silicon nitride material.

10. The method of claim 8 , wherein planarizing an opposing surface of a device wafer comprises planarizing the opposing surface of the device wafer to a total thickness variation (TTV) of between about 3 μm and about 8 μm.

11. The method of claim 8 , wherein applying a sacrificial material to a surface of a carrier wafer comprises applying a sacrificial material to a wafer comprising a semiconductor material or a glass material.

12. The method of claim 8 , wherein planarizing the opposing surface of the device wafer comprises reducing an initial thickness of the device wafer from at least 700 μm to less than 100 μm.

13. The method of claim 8 , wherein applying a sacrificial material to a surface of a carrier wafer comprises applying a sacrificial material to a thickness of between about 15 μm and about 30 μm.

14. The method of claim 13 , wherein removing only a portion of a thickness of the sacrificial material comprises removing between about 12 μm and about 15 μm of the thickness.

15. The method of claim 8 , further comprising:

securing the opposing surface of the device wafer to a support;

removing the carrier wafer from the device wafer; and

singulating semiconductor dice from the device wafer.

16. The method of claim 15 , wherein securing the opposing surface of the device wafer to a support comprises adhering the opposing surface of the device wafer to a film supported by a film frame.

17. The method of claim 15 , further comprising removing any remaining sacrificial material on the surface of the carrier wafer before removing the carrier wafer from the device wafer.

Assignments (7)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050709/0838 →
RELEASE OF SECURITY INTEREST Recorded Jul 20, 2018
From: U.S. BANK NATIONAL ASSOCIATION, AS AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 046597/0333 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
SUPPLEMENT NO. 6 TO PATENT SECURITY AGREEMENT Recorded Nov 1, 2017
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 044348/0253 →
SUPPLEMENT NO. 6 TO PATENT SECURITY AGREEMENT Recorded Nov 1, 2017
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 044653/0333 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 18, 2017
From: BAYLESS, ANDREW M.
To: MICRON TECHNOLOGY, INC.
Reel/Frame 043334/0225 →