Apparatuses and methods for storing redundancy repair information for memories

1. An apparatus, comprising:

a fuse array configured to store repair information, wherein the repair information includes repair commands and load repair addresses, wherein the load repair addresses include a respective repair address;

a first repair plane including a block of memory and repair logic, the block of memory including a plurality of redundant memory and the repair logic including a plurality of repair blocks, each repair block of the plurality of repair blocks associated with a respective one of the plurality of redundant memory and each repair block of the plurality of repair blocks configured to store a repair address;

a second repair plane including a block of memory and repair logic, the block of memory of the second repair plane including a plurality of redundant memory and the repair logic including a plurality of repair blocks, each repair block of the plurality of repair blocks associated with a respective one of the plurality of redundant memory and each repair block of the plurality of repair blocks configured to store a repair address; and

a decode logic and control circuit configured to read the repair information and decode the repair commands, and configured to load repair addresses into the plurality of repair blocks based at least in part on the decoded repair commands, the decode logic and control circuit is further configured to transfer a repair plane token from the first repair plane to the second repair plane responsive to a repair command to transfer the repair plane token to a next repair plane.

2. The apparatus of claim 1 wherein the load repair addresses includes a compressed repair address.

3. The apparatus of claim 2 wherein the decode logic and control circuit is configured to uncompress the compressed repair address and load the uncompressed repair address into a repair block.

4. The apparatus of claim 3 wherein the decode logic and control circuit is configured to uncompress a compressed repair address that is a “0” and load all zeros into the repair block.

5. The apparatus of claim 3 wherein the decode logic and control circuit is configured to interpret and execute the decoded repair commands.

6. The apparatus of claim 1 wherein the fuse array, first repair plane, and decode logic and control circuit are integrated into a semiconductor device.

7. The apparatus of claim 1 wherein the decode logic and control circuit is configured to load repair addresses into the plurality of repair blocks of the second repair plane following the transfer of the repair plane token to the second repair plane.

8. The apparatus of claim 1 wherein the decode logic and control circuit is configured to identify a repair command by a repair command prefix and to identify a load repair address by a load repair address prefix.

9. The apparatus of claim 8 wherein the decode logic and control circuit is configured to decode a command code following the repair command prefix for a repair command and to load a repair address following the load repair address prefix for a load repair address.

10. An apparatus, comprising:

a fuse array configured to store repair information;

a memory bus;

a controller coupled to the memory bus, the controller including a decode logic and control circuit, the decode logic and control circuit configured to read the repair information and translate the repair information into intermediate repair information and providing the intermediate repair information to the memory bus; and

a plurality of memory devices coupled to the memory bus, each memory device of the plurality of memory devices including:

primary memory and redundant memory;

repair logic including a plurality of repair blocks, each repair block of the plurality of repair blocks configured to store a repair flag and a repair address that is mapped to a respective redundant memory unit of the redundant memory; and

repair address and repair flag loading circuits configured to receive the intermediate repair information from the memory bus and further configured to load a repair address and repair flag set into a repair block of the plurality of repair blocks, wherein the repair address and repair flag set is based at least in part on the intermediate repair information.

11. The apparatus of claim 10 wherein the memory bus includes a Joint Test Action Group (JTAG) communication channel.

12. The apparatus of claim 11 wherein the controller is configured to translate the repair information into intermediate repair information including repair information chains meeting the protocol for the JTAG communication channel.

13. The apparatus of claim 10 wherein the fuse array and the controller are integrated in a semiconductor die and wherein the plurality of memory devices are stacked memory devices.

14. The apparatus of claim 10 wherein the repair information stored in the fuse array includes repair commands and load repair addresses, wherein the load repair addresses includes at least one compressed repair address.

15. The apparatus of claim 14 wherein the repair information includes repair commands and load repair addresses, wherein the repair commands each include a repair command prefix and command code and wherein at a load repair address includes a load repair address prefix and a repair address.