IP Library Granted Patent US 10,158,022
Granted Patent B2
US 10,158,022 · App. 15/681,417 · Granted Dec 18, 2018

Bottom-up epitaxy growth on air-gap buffer

Inventors: Sheng-Hsu Liu (Changhua County, TW); Jhen-cyuan Li (New Taipei, TW); Chih-Chung Chen (Tainan, TW); Man-Ling Lu (Taoyuan, TW); Chung-Min Tsai (Tainan, TW); Yi-Wei Chen (Taichung, TW)
Assignee: UNITED MICROELECTRONICS CORP.
H01L29/7851H01L21/764H01L29/0649H01L29/0692H01L29/165H01L29/66795H01L29/7848Y02E10/50
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Quick Facts
Patent No.
US 10,158,022
App. No.
15/681,417
Granted
Dec 18, 2018
Kind
B2
Abstract

A fin structure for a semiconductor device, such as a FinFET structure, has first and second semiconductor layers and an air gap between the layers. The second semiconductor layer includes a recessed portion, the air gap is located in the recessed portion, and the recessed portion has an upwardly-opening acute angle in the range from about 10° to about 55°. The air gap may prevent current leakage. A FinFET device may be manufactured by first recessing and then epitaxially re-growing a source/drain fin, with the regrowth starting over a tubular air gap.

Claims (27)

1. A fin structure for a semiconductor device, comprising:

a first semiconductor material;

an air gap; and

a second semiconductor material, wherein the second semiconductor material comprises a recessed portion, the air gap is located in the recessed portion, and the recessed portion has an upwardly-opening acute angle in the range from about 10° to about 55°;

wherein the air gap is located between the first semiconductor material and the second semiconductor material.

2. The fin structure of claim 1 , wherein the air gap has a tubular configuration.

3. The fin structure of claim 2 , wherein the fin structure is elongated in a first direction, the first semiconductor material extends in the first direction, and the air gap has a central axis that is parallel to the first direction.

4. The fin structure of claim 1 , wherein the air gap is located in the bottom of the recessed portion.

5. The fin structure of claim 1 , wherein the second semiconductor material includes single-crystal silicon.

6. The fin structure of claim 1 , wherein the first semiconductor material includes one or more of Si, phosphorus-doped Si, SiGe, SiC, and GaAs.

7. A fin-type field effect transistor (FinFET) device, comprising:

a substrate;

a fin having source and drain regions; and

a gate straddling the fin;

wherein the fin includes a first semiconductor material and an air gap;

wherein the substrate includes a second semiconductor material, different from the first semiconductor material;

wherein the second semiconductor material comprises a recessed portion, the air gap is located in the recessed portion, and the recessed portion has an upwardly-opening acute angle in the range from about 10° to about 55°; and

wherein the air gap is located between the first semiconductor material and the second semiconductor material.

8. The fin-type field effect transistor (FinFET) device of claim 7 , wherein the air gap has a tubular configuration.

9. The fin-type field effect transistor (FinFET) device of claim 8 , wherein the fin is elongated in a first direction, the gate is elongated in a second direction, orthogonal to the first direction, and the air gap has a central axis that is parallel to the first direction.

10. The fin-type field effect transistor (FinFET) device of claim 9 , wherein the first semiconductor material is located in the recessed portion, and the upwardly-opening acute angle is located in a plane that is perpendicular to the first direction.

11. The fin-type field effect transistor (FinFET) device of claim 7 , wherein the second semiconductor material includes single-crystal silicon.

12. The fin-type field effect transistor (FinFET) device of claim 7 , wherein the second semiconductor material includes one or more of Si, SiGe, SiC, and GaAs.

13. The fin-type field effect transistor (FinFET) device of claim 7 , further comprising walls for defining a source/drain recess, and wherein said first semiconductor material is located between the walls.

14. The fin-type field effect transistor (FinFET) device of claim 13 , wherein the walls include one or more hard mask and dielectric materials.

15. The fin-type field effect transistor (FinFET) device of claim 13 , wherein the first semiconductor material includes an SiP buffer layer, and wherein the device further comprises an SiP bulk layer located on the SiP buffer layer.

16. The fin-type field effect transistor (FinFET) device of claim 15 , further comprising a shovel-shape element, and wherein the shovel-shape element is part of the SiP bulk layer.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 26, 2021
From: UNITED MICROELECTRONICS CORPORATION
To: MARLIN SEMICONDUCTOR LIMITED
Reel/Frame 056991/0292 →
Continuity (2)
Continuation 15144204 · May 2, 2016
Related Publication 20170345938A1 · Nov 30, 2017