High density vertical thyristor memory cell array with improved isolation
Isolation between vertical thyristor memory cells in an array is improved with isolation regions between the vertical thyristor memory cells. The isolation regions are formed by electrically isolating cores surrounded by insulating material, such as silicon dioxide, in trenches between the memory cells. The electrically isolating cores may be tubes of air or conducting rods. Methods of constructing the isolation regions in a processes for manufacturing vertical thyristor memory cell arrays are also disclosed.
1. An integrated circuit having an array of vertical thyristor memory cells in a semiconductor substrate, each vertical thyristor memory cell separated from other vertical thyristor memory cells by isolation regions, each isolation region comprising:
a trench extending parallel to a surface of the semiconductor substrate and separating at least two pairs of vertical memory cells;
an electrically isolating core in the trench; and
insulating material enclosing the electrically isolating core in the trench, the insulating material and electrically isolating core occupying an entirety of the trench;
whereby the isolation region electrically isolates the vertical thyristor memory cell from interference by operations of neighboring memory cells.
2. The integrated circuit of claim 1 , wherein the electrically isolating core comprises an air tube along the trench.
3. The integrated circuit of claim 1 , wherein the insulating material comprises silicon dioxide.
4. An integrated circuit having a semiconductor substrate, comprising:
a first thyristor having a vertically stacked P-conductivity type anode, N-conductivity type base, P-conductivity type base, and N-conductivity cathode provided by the semiconductor substrate;
a second thyristor having a vertically stacked P-conductivity type anode, N-conductivity type base, P-conductivity type base, and N-conductivity cathode provided by the semiconductor substrate; and
an isolation region separating the first thyristor from the second thyristor, the isolation region including
a trench extending into the semiconductor substrate below a junction region between the P-conductivity type base and the N-conductivity cathode of each of the first and second thyristors, the trench extending parallel to a surface of the semiconductor substrate and separating at least two pairs of vertical thyristor memory cells;
an electrically isolating core; and
insulating material surrounding the electrically isolating core in the trench, the insulating material and electrically isolating core occupying an entirely of the trench;
whereby the isolation region electrically isolates the first and second thyristors from interference by operation of the other thyristor.
5. The integrated circuit of claim 4 , wherein the electrically isolating core comprises an air tube along the trench.
6. The integrated circuit of claim 4 , wherein the insulating material comprises silicon dioxide.