IP Library Granted Patent US 10,277,212
Granted Patent B2
US 10,277,212 · App. 15/683,998 · Granted Apr 30, 2019

Pulse generator and driving circuit comprising the same

Inventors: Kinam Song (Seoul, KR); Wonhi Oh (Bucheon-si, KR); Jinkyu Choi (Bucheon-si, KR); Tae-sung Kwon (Seoul, KR); Seunghyun Hong (Seoul, KR)
Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
H03K5/12H03K19/0013H03K19/00369H03K19/0175H03K19/017509
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Quick Facts
Patent No.
US 10,277,212
App. No.
15/683,998
Granted
Apr 30, 2019
Kind
B2
Abstract

A pulse generator includes a first inverter configured to inverse an input pulse and output a result, a second inverter configured to inverse the output of the first inverter and output a result, a clamp inverter configured to generate a clamping voltage by clamping the output of the second inverter and generate an output pulse through a source follower which operates according to the clamping voltage, and a temperature compensator configured to compensate for variations in the clamping voltage caused by temperature change.

Claims (45)

1. A driving circuit comprising:

a pulse generator comprising a first Zener diode and a source follower, the pulse generator being configured to clamp a signal corresponding to an input pulse through the first Zener diode and generate a clamping voltage, wherein the source follower is configured to operate according to the clamping voltage to generate an output pulse; and

a level shifter comprising a high voltage device coupled between a high voltage and a ground, wherein the high voltage device is configured to switch according to the output pulse to shift a level of the output pulse and output a result,

wherein the source follower comprises a first transistor comprising a gate to which the clamping voltage is inputted, a first electrode coupled to an output node of the pulse generator, and a second electrode coupled to a power supply voltage, the power supply voltage having a level greater than a ground level.

2. The driving circuit of claim 1 , wherein the pulse generator further comprises a second transistor coupled between the output node of the pulse generator and a ground, and wherein the second transistor is configured to switch according to a signal which is inverted from the input pulse.

3. The driving circuit of claim 1 , wherein the signal corresponding to the input pulse is supplied to a cathode of the first Zener diode, and

wherein the pulse generator further comprises a temperature compensator which is coupled to an anode of the first Zener diode and has a polarity opposite to a temperature coefficient polarity of the first Zener diode.

4. The driving circuit of claim 3 , wherein the temperature compensator comprises a second transistor that is diode-connected, the second transistor comprising a first electrode coupled to a ground, and a second electrode coupled to the anode of the first Zener diode.

5. The driving circuit of claim 4 , wherein a threshold voltage of the first transistor is substantially equal to a threshold voltage of the second transistor.

6. The driving circuit of claim 3 , wherein the temperature compensator comprises at least one or more diodes, and an anode of the at least one or more diodes is coupled to the anode of the first Zener diode.

7. The driving circuit of claim 1 , wherein the pulse generator further comprises:

a second transistor coupled between the power supply voltage and a cathode of the first Zener diode, wherein the second transistor is to switch according to a signal which is inverted from the input pulse; and

a current source coupled between the power supply voltage and the second transistor to supply constant current.

8. The driving circuit of claim 1 , wherein the output pulse has a level that is substantially equal to a Zener voltage of the first Zener diode when the output pulse has the first logic level.

9. A driving circuit comprising:

a first inverter configured to invert an input pulse and output a result;

a second inverter configured to invert the output of the first inverter and output a result;

a clamp inverter configured to generate a clamping voltage by clamping the output of the second inverter and generate an output pulse through a source follower which operates according to the clamping voltage;

a level shifter comprising a high voltage device coupled between a high voltage and a ground, wherein the high voltage device is configured to switch according to the output pulse to shift a level of the output pulse and output a result; and

a temperature compensator configured to compensate for variations in the clamping voltage caused by a temperature change,

wherein the clamp inverter comprises a first Zener diode coupled between the output of the second inverter and the temperature compensator, and

wherein the temperature compensator is coupled to an anode of the first Zener diode, and has a polarity opposite to a temperature coefficient of the first Zener diode according to a temperature rise.

10. The driving circuit of claim 9 , wherein the temperature compensator comprises a transistor which is diode-connected, the transistor comprising a first electrode coupled to the ground, a second electrode coupled to the anode of the first Zener diode.

11. The driving circuit of claim 9 , wherein the temperature compensator further comprises a plurality of diodes coupled between the output of the second inverter and a ground, and

wherein the clamp inverter further comprises a first transistor comprising a gate coupled to the output of the second inverter, a first electrode coupled to an output node of the clamp inverter, and a second electrode coupled to a first voltage, wherein the first transistor is configured to implement the source follower.

12. The driving circuit of claim 9 , wherein the clamp inverter further comprises:

a current source coupled between the output of the second inverter and a ground; and

a first transistor comprising a gate coupled to the output of the second inverter, a first electrode coupled to an output node of the clamp inverter, and a second electrode coupled to a first voltage, wherein the first transistor is configured to implement the source follower.

13. A method of operating an electrical circuit, the method comprising:

inverting an input pulse to generate a first output signal;

inverting the first output signal to generate a second output signal;

clamping the second output signal to generate a clamping voltage; and

coupling a power supply voltage through a transistor to a node at which an output pulse is generated;

controlling a switching operation of a high voltage device of a level shifter based on the output pulse, the power supply voltage having a level greater than a ground level,

wherein the transistor comprises a gate receiving the clamping voltage, a first electrode coupled to the node at which the output pulse is generated, and a second electrode coupled to the power supply voltage.

14. The method of claim 13 , further comprising:

compensating for variations in the clamping voltage caused by a temperature change.

15. The method of claim 14 , wherein compensating for variations in the clamping voltage caused by the temperature change comprises:

decreasing current flowing through a Zener diode that provides the clamping voltage as the temperature increases.

16. The method of claim 15 , wherein decreasing the current flowing through the Zener diode comprises:

decreasing a gate-to-source voltage of a transistor coupled to an anode of the Zener diode as the temperature increases.

17. The method of claim 15 , wherein decreasing the current flowing through the Zener diode comprises:

decreasing current flowing through one or more diodes that are connected to an anode of the Zener diode as the temperature increases.

18. The method of claim 14 , wherein compensating for variations in the clamping voltage caused by the temperature change comprises:

decreasing current flowing through a plurality of diodes that provide the clamping voltage as the temperature increases.

Assignments (4)
RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT REEL 046530, FRAME 0460 Recorded Jun 23, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 064075/0001 →
PATENT SECURITY AGREEMENT Recorded Jul 11, 2018
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 046530/0460 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 2, 2017
From: FAIRCHILD KOREA SEMICONDUCTOR, LTD.
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 044361/0205 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 23, 2017
From: SONG, KINAM; OH, WONHI; CHOI, JINKYU; KWON, TAESUNG; HONG, SEUNGHYUN
To: FAIRCHILD KOREA SEMICONDUCTOR LTD.
Reel/Frame 043646/0407 →
Priority Claims (1)
KR 10-2015-0050485 · Apr 9, 2015 · national
Continuity (3)
Division 14699732 · Apr 29, 2015
Provisional Application 61986261 · Apr 30, 2014
Related Publication 20170373673A1 · Dec 28, 2017