IP Library Granted Patent US 10,163,685
Granted Patent B2
US 10,163,685 · App. 15/684,080 · Granted Dec 25, 2018

Methods of forming one or more covered voids in a semiconductor substrate

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Quick Facts
Patent No.
US 10,163,685
App. No.
15/684,080
Granted
Dec 25, 2018
Kind
B2
Abstract

Some embodiments include methods of forming voids within semiconductor constructions. In some embodiments the voids may be utilized as microstructures for distributing coolant, for guiding electromagnetic radiation, or for separation and/or characterization of materials. Some embodiments include constructions having micro-structures therein which correspond to voids, conduits, insulative structures, semiconductor structures or conductive structures.

Claims (9)

1. A method of forming a covered void in a semiconductor substrate, comprising:

forming a pair of projections projecting upwardly from a semiconductor substrate, the projections comprising sidewalls;

providing elemental-form silicon atop the pair of projections; and

selectively growing relative to at least portions of the projection sidewalls at least one of elemental-form W or a silicide from the elemental-form silicon to bridge across the pair of projections to form a covered void between the pair of projections.

2. The method of claim 1 wherein the selectively growing comprises selectively growing elemental-form W.

3. The method of claim 1 wherein the selectively growing comprises selectively growing a silicide.

4. The method of claim 1 comprising providing the elemental-form silicon to comprise amorphous silicon.

5. The method of claim 1 comprising providing the elemental-form silicon to comprise monocrystalline silicon.

6. The method of claim 1 comprising forming the pair of projections to comprise spaced free-standing pillars prior to said selectively growing.

Assignments (6)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050709/0838 →
RELEASE OF SECURITY INTEREST Recorded Jul 20, 2018
From: U.S. BANK NATIONAL ASSOCIATION, AS AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 046597/0333 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
SUPPLEMENT NO. 6 TO PATENT SECURITY AGREEMENT Recorded Nov 1, 2017
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 044348/0253 →
SUPPLEMENT NO. 6 TO PATENT SECURITY AGREEMENT Recorded Nov 1, 2017
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 044653/0333 →