IP Library Granted Patent US 10,153,197
Granted Patent B2
US 10,153,197 · App. 15/684,728 · Granted Dec 11, 2018

Methods of forming one or more covered voids in a semiconductor substrate

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Quick Facts
Patent No.
US 10,153,197
App. No.
15/684,728
Granted
Dec 11, 2018
Kind
B2
Abstract

Some embodiments include methods of forming voids within semiconductor constructions. In some embodiments the voids may be utilized as microstructures for distributing coolant, for guiding electromagnetic radiation, or for separation and/or characterization of materials. Some embodiments include constructions having micro-structures therein which correspond to voids, conduits, insulative structures, semiconductor structures or conductive structures.

Claims (12)

1. Integrated circuitry comprising:

a semiconductor-on-insulator substrate having a mean outermost global surface; the substrate comprising monocrystalline silicon-containing material, an insulator material over the monocrystalline silicon-containing material, and first elemental-form silicon-comprising material over the insulator material;

a plurality of elongated cooling conduits running generally parallel the mean outermost global surface within the insulator material, the cooling conduits individually comprising opposing sidewalls of the insulator material, the cooling conduits individually comprising a top of second elemental-form silicon-comprising material, the cooling conduits individually comprising a bottom of third elemental-form silicon-comprising material; and

cooling fluid within the cooling conduits.

2. The integrated circuitry of claim 1 wherein the cooling fluid is flowing within the cooling conduits.

3. The integrated circuitry of claim 1 comprising field effect transistor channel regions within the second elemental-form silicon-comprising material that is over the cooling conduits.

4. The integrated circuitry of claim 1 comprising field effect transistor source/drain regions within the second elemental-form silicon-comprising material that is over the cooling conduits.

5. The integrated circuitry of claim 1 comprising field effect transistor channel regions and field effect transistor source/drain regions within the second elemental-form silicon-comprising material that is over the cooling conduits.

6. The integrated circuitry of claim 3 wherein the cooling fluid within the cooling conduits is in physical touching contact with the channel regions.

7. The integrated circuitry of claim 5 wherein the cooling fluid within the cooling conduits is in physical touching contact with the channel regions.

8. The integrated circuitry of claim 1 wherein the insulator material comprises silicon dioxide.

9. The integrated circuitry of claim 1 wherein the insulator material comprises silicon nitride.

Assignments (6)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050709/0838 →
RELEASE OF SECURITY INTEREST Recorded Jul 20, 2018
From: U.S. BANK NATIONAL ASSOCIATION, AS AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 046597/0333 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
SUPPLEMENT NO. 6 TO PATENT SECURITY AGREEMENT Recorded Nov 1, 2017
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 044348/0253 →
SUPPLEMENT NO. 6 TO PATENT SECURITY AGREEMENT Recorded Nov 1, 2017
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 044653/0333 →