On demand memory page size
View Patent ↗Systems, devices, and methods related to on demand memory page size are described. A memory system may employ a protocol that supports on demand variable memory page sizes. A memory system may include one or more non-volatile memory devices that may each include a local memory controller configured to support variable memory page size operation. The memory system may include a system memory controller that interfaces between the non-volatile memory devices and a processor. The system memory controller may, for instance, use a protocol that facilitates on demand memory page size where a determination of a particular page size to use in an operation may be based on characteristics of memory commands and data involved in the memory command.
1. A method, comprising:
receiving, at a system memory controller from a processor, a memory access request that comprises a first set of parameters indicative of a memory page size, wherein the system memory controller is coupled to the processor and a local memory controller associated with a memory array;
configuring a memory access command based at least in part on receiving the memory access request, wherein the memory access command comprises a second set of parameters indicative of the memory page size and an identification of the memory array, the second set of parameters based at least in part on the first set of parameters; and
sending, to the local memory controller, the memory access command with the second set of parameters, wherein the local memory controller is configured to determine the memory page size based at least in part on the second set of parameters, wherein:
the first set of parameters comprises an address indicating a location of data to access and a number of bits determinative of the memory page size; and
the second set of parameters comprises the identification of the memory array, the address associated with the memory array, and the memory page size for the local memory controller.
2. The method of claim 1 , wherein:
the first set of parameters comprises an indication of data for an access operation and a size of the data; and
the second set of parameters comprises the identification of the memory array, the address associated with the memory array, and the size of the data.
3. The method of claim 1 , wherein:
the first set of parameters comprises a beginning address and an ending address for the memory array; and
the second set of parameters comprises the identification of the memory array, the beginning address, and the ending address associated with the memory array.
4. The method of claim 1 , wherein the first set of parameters comprises an indicator of a relationship between contents of the bits and the memory page size.
5. The method of claim 1 , wherein:
the first set of parameters comprises the address associated with a pre-determined memory page size; and
the second set of parameters comprises the identification of the memory array, the address associated with the memory array, and the pre-determined memory page size for the local memory controller.
6. The method of claim 5 , wherein the pre-determined memory page size is selected from a plurality of memory page sizes based at least in part on the address, and the first set of parameters comprises an indication of a relationship between the address and the pre-determined memory page size.
7. A system, comprising:
a processor;
a local memory controller associated with a memory array; and
a system memory controller in electronic communication with the processor and the local memory controller, wherein the system memory controller is operable to:
receive, from the processor, a memory access request comprising a first set of parameters indicative of a memory page size;
configure a memory access command based at least in part on receiving the memory access request, wherein the memory access command comprises a second set of parameters indicative of the memory page size and an identification of the memory array, the second set of parameters based at least in part on the first set of parameters; and
send, to the local memory controller, the memory access command with the second set of parameters, wherein the local memory controller is configured to determine the memory page size based at least in part on the second set of parameters, wherein:
the first set of parameters comprises an address indicating a location of data to access and a number of bits determinative of the memory page size; and
the second set of parameters comprises the identification of the memory array, the address associated with the memory array, and the memory page size for the local memory controller.
8. The system of claim 7 , wherein:
the first set of parameters comprises an indication of data for an access operation and a size of the data; and
the second set of parameters comprises the identification of the memory array, the address associated with the memory array, and the size of the data.
9. The system of claim 7 , wherein:
the first set of parameters comprises a beginning address and an ending address for the memory array; and
the second set of parameters comprises the identification of the memory array, the beginning address, and the ending address associated with the memory array.
10. The system of claim 7 , wherein the first set of parameters comprises an indicator of a relationship between contents of the bits and the memory page size.
11. The system of claim 7 , wherein:
the first set of parameters comprises the address associated with a pre-determined memory page size; and
the second set of parameters comprises the identification of the memory array, the address associated with the memory array, and the pre-determined memory page size for the local memory controller.
12. The system of claim 11 , wherein the pre-determined memory page size is selected from a plurality of memory page sizes based at least in part on the address, and the first set of parameters comprises an indication of a relationship between the address and the pre-determined memory page size.