IP Library Granted Patent US 10,261,123
Granted Patent B2
US 10,261,123 · App. 15/685,997 · Granted Apr 16, 2019

Semiconductor device structures for burn-in testing and methods thereof

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Quick Facts
Patent No.
US 10,261,123
App. No.
15/685,997
Granted
Apr 16, 2019
Kind
B2
Abstract

A semiconductor device structure is provided. The semiconductor device structure includes a substrate, an electrical connection structure extending upwardly from an upper surface of the substrate by a first height, and a contact pad electrically disposed on the upper surface of the substrate. The contact pad has a solder-wettable surface with an area configured to support a solder ball having a second height at least twice the first height. The semiconductor device structure further includes a fuse element with a first end electrically coupled to the electrical connection structure and a second end electrically coupled to the contact pad.

Claims (35)

1. A semiconductor device structure, comprising:

a substrate;

an electrical connection structure extending upwardly from an upper surface of the substrate by a first height;

a contact pad electrically disposed on the upper surface of the substrate, the contact pad having a solder-wettable surface with an area configured to support a solder ball having a second height at least twice the first height; and

a fuse element with a first end electrically coupled to the electrical connection structure and a second end electrically coupled to the contact pad.

2. The semiconductor device structure of claim 1 , wherein the first height is between about 5 and 30 μm.

3. The semiconductor device structure of claim 1 , wherein the second height is greater than about 50 μm.

4. The semiconductor device structure of claim 1 , wherein the electrical connection structure is a copper pillar having a diameter of between about 5 and 30 μm.

5. The semiconductor device structure of claim 1 , wherein the area of the contact pad is a circle with a diameter of between about 10 and 50 μm.

6. The semiconductor device structure of claim 1 , wherein the fuse element is laser-blowable fuse.

7. The semiconductor device structure of claim 6 , wherein the laser-blowable fuse is proximate to the electrical connection structure.

8. The semiconductor device structure of claim 1 , wherein the fuse element is a blown fuse element.

9. A semiconductor device structure, comprising:

a substrate;

a plurality of electrical connection structures extending upwardly from an upper surface of the substrate by a first height;

a plurality of contact pads disposed on the upper surface of the substrate on opposing sides of the plurality of electrical connection structures, each contact pad having a solder-wettable surface with an area configured to support a solder ball having a second height at least twice the first height; and

a plurality of fuse elements, each fuse element having a first end electrically coupled to a corresponding one of the plurality of electrical connection structures and a second end electrically coupled to a corresponding one of the plurality of contact pads.

10. The semiconductor device structure of claim 9 , wherein the first height is between about 5 and 30 μm.

11. The semiconductor device structure of claim 9 , wherein the second height is greater than about 50 μm.

12. The semiconductor device structure of claim 9 , wherein the plurality of electrical connection structures comprise a plurality of copper pillars each having a diameter of between about 5 and 30 μm.

13. The semiconductor device structure of claim 9 , wherein the area of each of the plurality of contact pads is a circle with a diameter of between about 10 and about 50 μm.

14. The semiconductor device structure of claim 9 , wherein the plurality of fuse elements comprise a plurality of laser-blowable fuses.

15. The semiconductor device structure of claim 14 , wherein each laser-blowable fuses is proximate to the corresponding one of the plurality of electrical connection structures.

16. The semiconductor device structure of claim 9 , wherein the plurality of fuse elements comprise a plurality of blown fuse elements.

17. A method of testing a semiconductor device including a substrate with a plurality of electrical connection structures extending upwardly from an upper surface of the substrate by a first height, the method comprising:

disposing, on a plurality of contact pads electrically coupled to corresponding ones of the plurality of electrical connection structures and disposed on the upper surface of the substrate, a corresponding plurality of solder balls having a second height at least twice the first height;

connecting, to the plurality of solder balls, a test structure; and

electrically testing circuits of the semiconductor device through the test structure.

18. The method according to claim 17 , wherein connecting the test structure comprises reflowing the solder balls to form solder junctions between the plurality of contact pads and the test structure.

19. The method according to claim 17 , wherein the test structure is supported by the solder junctions a third height above the plurality of electrical connection structures.

20. The method according to claim 17 , further comprising reflowing the solder junctions to remove the test structure.

21. The method according to claim 17 , further comprising removing the test structure and removing remaining solder from the plurality of contact pads.

22. The method according to claim 17 , further comprising electrically decoupling the plurality of contact pads from the plurality of electrical connection structures.

23. The method according to claim 17 , wherein first height is between about 5 and 30 μm.

24. The method according to claim 17 , wherein the circuits are electrically tested in a burn-in oven.

Assignments (7)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050709/0838 →
RELEASE OF SECURITY INTEREST Recorded Jul 20, 2018
From: U.S. BANK NATIONAL ASSOCIATION, AS AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 046597/0333 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 13, 2017
From: TUTTLE, MARK E.
To: MICRON TECHNOLOGY, INC.
Reel/Frame 044390/0955 →
SUPPLEMENT NO. 6 TO PATENT SECURITY AGREEMENT Recorded Nov 1, 2017
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 044348/0253 →
SUPPLEMENT NO. 6 TO PATENT SECURITY AGREEMENT Recorded Nov 1, 2017
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 044653/0333 →