Conformal low temperature hermetic dielectric diffusion barriers
Conformal hermetic dielectric films suitable as dielectric diffusion barriers over 3D topography. In embodiments, the dielectric diffusion barrier includes a dielectric layer, such as a metal oxide, which can be deposited by atomic layer deposition (ALD) techniques with a conformality and density greater than can be achieved in a conventional silicon dioxide-based film deposited by a PECVD process for a thinner contiguous hermetic diffusion barrier. In further embodiments, the diffusion barrier is a multi-layered film including a high-k dielectric layer and a low-k or intermediate-k dielectric layer (e.g., a bi-layer) to reduce the dielectric constant of the diffusion barrier. In other embodiments a silicate of a high-k dielectric layer (e.g., a metal silicate) is formed to lower the k-value of the diffusion barrier by adjusting the silicon content of the silicate while maintaining high film conformality and density.
1. An integrated circuit structure, comprising:
a first interconnect structure comprising a metal, the first interconnect structure in a first low-k inter-layer dielectric (ILD) layer above a substrate;
a second interconnect structure comprising a metal, the second interconnect structure in the first low-k ILD layer above the substrate;
a trench in the first low-k ILD layer between the first interconnect structure and the second interconnect structure, the trench having a bottom and sidewalls;
a dielectric diffusion barrier layer continuous over a portion of the first interconnect structure, continuous over a portion of the second interconnect structure and continuous along the bottom and sidewalls of the trench;
a second low-k ILD layer on the dielectric diffusion barrier layer along the bottom and sidewalls of the trench; and
an air gap in the second low-k ILD layer, the air gap having a top below a portion of the top of the dielectric diffusion barrier layer over the portion of the first interconnect structure.
2. The integrated circuit structure of claim 1 , further comprising:
a hardmask layer between the dielectric diffusion barrier layer and the first interconnect structure.
3. The integrated circuit structure of claim 2 , wherein the hardmask layer is not in the trench.
4. The integrated circuit structure of claim 2 , wherein the hardmask layer comprises silicon, oxygen and nitrogen.
5. The integrated circuit structure of claim 1 , wherein the air gap is entirely within the second low-k ILD layer.
6. The integrated circuit structure of claim 1 , wherein the first low-k ILD layer has a dielectric constant in the range of 2.5-3.2.
7. The integrated circuit structure of claim 6 , wherein the first low-k ILD layer comprises silicon, oxygen, carbon and hydrogen.
8. The integrated circuit structure of claim 1 , wherein the second low-k ILD layer has a dielectric constant in the range of 2.5-3.1.
9. The integrated circuit structure of claim 8 , wherein the second low-k ILD layer comprises silicon, oxygen, carbon and hydrogen.
10. The integrated circuit structure of claim 1 , wherein the dielectric diffusion barrier layer has a dielectric constant greater than the dielectric constant of the first low-k ILD layer and greater than the dielectric constant of the second low-k ILD layer.
11. A method of fabricating an integrated circuit structure, the method comprising:
forming a first interconnect structure comprising a metal, the first interconnect structure in a first low-k inter-layer dielectric (ILD) layer above a substrate;
forming a second interconnect structure comprising a metal, the second interconnect structure in the first low-k ILD layer above the substrate;
forming a trench in the first low-k ILD layer between the first interconnect structure and the second interconnect structure, the trench having a bottom and sidewalls;
forming a dielectric diffusion barrier layer continuous over a portion of the first interconnect structure, continuous over a portion of the second interconnect structure and continuous along the bottom and sidewalls of the trench;
forming a second low-k ILD layer on the dielectric diffusion barrier layer along the bottom and sidewalls of the trench; and
forming an air gap in the second low-k ILD layer, the air gap having a top below a portion of the top of the dielectric diffusion barrier layer over the portion of the first interconnect structure.
12. The method of claim 11 , further comprising:
forming a hardmask layer between the dielectric diffusion barrier layer and the first interconnect structure.
13. The method of claim 12 , wherein the hardmask layer is not in the trench.
14. The method of claim 11 , wherein the hardmask layer comprises silicon, oxygen and nitrogen.
15. The method of claim 11 , wherein the air gap is entirely within the second low-k ILD layer.
16. The method of claim 11 , wherein the first low-k ILD layer has a dielectric constant in the range of 2.5-3.2.
17. The method of claim 16 , wherein the first low-k ILD layer comprises silicon, oxygen, carbon and hydrogen.
18. The method of claim 11 , wherein the second low-k ILD layer has a dielectric constant in the range of 2.5-3.1.
19. The method of claim 18 , wherein the second low-k ILD layer comprises silicon, oxygen, carbon and hydrogen.
20. The method of claim 11 , wherein the dielectric diffusion barrier layer has a dielectric constant greater than the dielectric constant of the first low-k ILD layer and greater than the dielectric constant of the second low-k ILD layer.