Arrays of cross-point memory structures
Some embodiments include a memory array having a first set of lines extending along a first direction, and a second set of lines over the first set of lines and extending along a second direction. Lines of the second set cross lines of the first set at cross-point locations. Memory structures are within the cross-point locations. Each memory structure includes a top electrode material, a bottom electrode material and a programmable material. Rails of insulative material extend parallel to the lines of the second set and alternate with the lines of the second set along the first direction. The programmable material has first regions within the memory structures and second regions over the rails of insulative material. A planarized surface extends across the lines of the second set and across the second regions of the programmable material. Some embodiments include methods of forming memory arrays.
1. A memory array, comprising:
a first set of lines extending along a first direction;
a second set of lines over the first set of lines, with individual lines of the second set crossing individual lines of the first set at cross-point locations;
memory structures between the lines of the first and second sets at the cross-point locations; each memory structure comprising a top electrode material, a bottom electrode material and a programmable material between the top and bottom electrode materials;
rails of insulative material extending parallel to the lines of the second set and alternating with the lines of the second set along the first direction;
the programmable material having first regions within the memory structures and having second regions over the rails of insulative material; and
a planarized surface extending across the lines of the second set and across the second regions of the programmable material.
2. The memory array of claim 1 comprising select devices between the lines of the first set and the memory structures.
3. The memory array of claim 2 wherein the select devices are diodes.
4. The memory array of claim 1 wherein a ratio of a thickness of the top electrode material along a vertical direction extending through the individual memory structures to a thickness of the bottom electrode material along the vertical direction extending through the individual memory structures is at least about 150.
5. The memory array of claim 1 wherein the memory structures are capacitors.
6. The memory array of claim 1 wherein the memory structures are ferroelectric capacitors.
7. The memory array of claim 1 wherein the insulative material of the rails comprises silicon dioxide.
8. A memory array, comprising:
a first set of lines extending along a first direction;
a second set of lines over the first set of lines and extending along a second direction substantially orthogonal to the first direction; the lines of the second set crossing the lines of the first set at cross-point locations; the lines of the second set being spaced from one another along the first direction by intervening regions;
memory structures between the lines of the first and second sets at the cross-point locations; each memory structure comprising a top electrode material, a bottom electrode material and a programmable material between the top and bottom electrode materials; wherein a ratio of a thickness of the top electrode material along a vertical direction extending through the individual memory structures to a thickness of the bottom electrode material along the vertical direction extending through the individual memory structures is at least about 150;
rails of insulative material within the intervening regions and extending parallel to the lines of the second set;
the programmable material having first regions within the memory structures and having second regions within the intervening regions and over the rails of insulative material; the programmable material having an undulating configuration which includes the second regions vertically displaced relative to the first regions; and
the top electrode material being configured as linear structures extending along the second direction, and having upwardly-opening linear trenches extending therein; the second lines being within said upwardly-opening linear trenches.
9. The memory array of claim 8 having a planarized surface extending across the lines of the second set and across the second regions of the programmable material.
10. The memory array of claim 9 wherein said planarized surface also extends across upper surfaces of the linear structures of the top electrode material.
11. The memory array of claim 8 wherein the programmable material comprises ferroelectric material.
12. The memory array of claim 8 wherein the lines of the first set are wordlines, and the lines of the second set are digit lines.
13. The memory array of claim 8 wherein the insulative material of the rails comprises silicon dioxide.