IP Library Granted Patent US 10,325,917
Granted Patent B2
US 10,325,917 · App. 15/686,107 · Granted Jun 18, 2019

Integrated structures and methods of forming integrated structures

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Quick Facts
Patent No.
US 10,325,917
App. No.
15/686,107
Granted
Jun 18, 2019
Kind
B2
Abstract

Some embodiments include an integrated structure having semiconductor material within a region between two parallel surfaces. The semiconductor material has grain boundaries parallel to the parallel surfaces. At least one circuit component utilizes a region of the semiconductor material in a gated device. The semiconductor material has little if any metal therein so that the gated device has Ion/Ioff characteristics similar to if the semiconductor material had no metal therein. Some embodiments include a method in which semiconductor material is provided between a pair of parallel surfaces, and in which the parallel surfaces and semiconductor material extend between a first end and a second end. Metal is formed adjacent the first end, and gettering material is formed adjacent the second end. Thermal processing induces crystallization of the semiconductor material and drives the metal along the semiconductor material and into the gettering material. The gettering material is then removed.

Claims (14)

1. A method of forming an integrated structure, comprising:

providing a configuration having semiconductor material between a pair of parallel surfaces, the configuration being a U-shaped NAND string with the parallel surfaces being U-shaped and on opposing sides of a channel region; the semiconductor material having a first crystallographic texture; the parallel surfaces and semiconductor material extending between a first end along one side of the U-shape and a second end along another side of the U-shape;

forming metal adjacent the first end, the metal comprising one or more metals selected from the group consisting of aluminum, near-noble metal and noble metal;

thermal processing the semiconductor material with the metal therein, the metal inducing crystallization of the semiconductor material to transition the first crystallographic texture to a second crystallographic texture;

forming a first region of gettering material across the first and second ends, and forming a second region of the gettering material across the first region of the gettering material;

thermal processing the semiconductor material and the first and second regions of the gettering material; thermodynamics driving the metal from the semiconductor material into the first gettering region, and then from the first gettering region to the second gettering region; and

removing the first and second gettering regions.

2. The method of claim 1 wherein the metal comprises aluminum.

3. The method of claim 1 wherein the metal comprises near-noble metal.

4. The method of claim 1 wherein the metal comprises noble metal.

5. The method of claim 1 wherein the first and second regions of gettering material are comprised by two or more distinct layers.

6. The method of claim 1 wherein the first region of the gettering material has a higher amorphous-to-crystal transition temperature than the semiconductor channel material and the second region of the gettering material.

7. The method of claim 6 wherein the gettering material comprises at least one additional region between the first and second regions; and wherein said at least one additional region has a lower amorphous-to-crystal transition temperature than the first region of the gettering material and a higher amorphous-to-crystal transition temperature than the second region of the gettering material.

8. The method of claim 1 wherein the first and second regions of gettering material are comprised by a structure having a first stoichiometry in the first gettering region, a second stoichiometry in the second gettering region, and a gradient from the first gettering region to the second gettering region; the first stoichiometry transitioning to the second stoichiometry along said gradient.

Assignments (6)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050709/0838 →
RELEASE OF SECURITY INTEREST Recorded Jul 20, 2018
From: U.S. BANK NATIONAL ASSOCIATION, AS AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 046597/0333 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
SUPPLEMENT NO. 6 TO PATENT SECURITY AGREEMENT Recorded Nov 1, 2017
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 044348/0253 →
SUPPLEMENT NO. 6 TO PATENT SECURITY AGREEMENT Recorded Nov 1, 2017
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 044653/0333 →