Buried contact to provide reduced VFET feature-to-feature tolerance requirements
Embodiments are directed to a semiconductor device. The semiconductor device includes a first semiconductor fin formed opposite a surface of a first active region of a substrate. The semiconductor device further includes a second semiconductor fin formed opposite a surface of a second active region of the substrate. The semiconductor device further includes a self-aligned buried contact formed over portions of the first active region and the second active region and between the first semiconductor fin and the second semiconductor fin.
1. A semiconductor device comprising:
a first semiconductor fin formed opposite a surface of a first active region of a substrate, the first active region comprising a first dopant type;
a second semiconductor fin formed opposite a surface of a second active region of the substrate, the second active region comprising a second dopant type complementary to the first dopant type;
a first gate formed over the first active region of the substrate, the first gate on a sidewall of the first semiconductor fin;
a second gate formed over the second active region of the substrate, the second gate on a sidewall of the second semiconductor fin;
a self-aligned buried contact formed over recessed portions of the first active region and the second active region and between the first semiconductor fin and the second semiconductor fin;
a dielectric layer formed over portions of the self-aligned buried contact, the dielectric layer comprising a first dielectric material formed on the first gate;
a spacer between the first gate and the self-aligned buried contact, wherein a spacer material included in the spacer has an etch selectivity relative to the first dielectric material; and
a contact formed in the dielectric layer, the contact positioned in direct contact with a topmost surface of the self-aligned buried contact and a topmost surface of the first gate.
2. The semiconductor device of claim 1 , wherein the spacer has a thickness of about 5 nanometers to about 12 nanometers.
3. The semiconductor device of claim 1 , wherein the spacer is formed on a sidewall of the dielectric layer comprising the first dielectric material and a sidewall of the first gate.
4. A semiconductor device comprising:
a substrate comprising a first active region and a second active region, the first active region comprising a first dopant type and the second active region comprising a second dopant type complementary to the first dopant type;
a first gate formed opposite a surface of the first active region;
a second gate formed opposite a surface of the second active region;
a buried contact formed over recessed portions of the first active region and the second active region;
a dielectric layer formed over portions of the buried contact, the dielectric layer comprising a first dielectric material formed on the first gate;
a dielectric spacer formed on the first active region and between the buried contact and the first gate, the dielectric spacer comprising a second dielectric material having an etch selectivity relative to the first dielectric material; and
a contact formed in the dielectric layer, the contact positioned on a topmost surface of the buried contact and on a topmost surface of the first gate.
5. The semiconductor device of claim 4 , wherein the dielectric spacer has a thickness of about 5 nanometers to about 12 nanometers.
6. The semiconductor device of claim 4 , wherein the dielectric spacer is formed on a sidewall of the dielectric layer comprising the first dielectric material and a sidewall of the first gate.