Method for source/drain contact formation in semiconductor devices
A method includes providing a structure that includes a substrate; first and second gate structures over the substrate; first and second source/drain (S/D) features over the substrate; a first dielectric layer over sidewalls of the first and second gate structures and the first and second S/D features; and a second dielectric layer over the first dielectric layer. The first and second S/D features are adjacent to the first and second gate structures respectively. The first and second S/D features comprise different materials. The method further includes etching the first and second dielectric layers to expose the first and second S/D features; doping a p-type dopant to the first and second S/D features; and performing a selective etching process to the first and second S/D features after the doping of the p-type dopant. The selective etching process recesses the first S/D feature faster than it recesses the second S/D feature.
1. A method of forming a semiconductor device, the method comprising:
providing a structure that includes:
a substrate;
a first gate structure and a second gate structure over the substrate;
a first source/drain (S/D) feature and a second S/D feature over the substrate, wherein the first S/D feature is adjacent to the first gate structure, the second S/D feature is adjacent to the second gate structure, and the first and second S/D features comprise different materials;
a first dielectric layer over sidewalls of the first and second gate structures and over the first and second S/D features; and
a second dielectric layer over the first dielectric layer;
etching the first and second dielectric layers to expose the first and second S/D features;
doping a p-type dopant into the first and second S/D features; and
after the doping of the p-type dopant, performing a selective etching process to the first and second S/D features, wherein the selective etching process recesses the first S/D feature faster than it recesses the second S/D feature.
2. The method of claim 1 , wherein the first S/D feature comprises silicon or silicon-carbon doped with an n-type dopant, and the second S/D feature comprises silicon germanium.
3. The method of claim 2 , wherein the n-type dopant is phosphorus or arsenic and the p-type dopant is boron.
4. The method of claim 3 , wherein the selective etching process includes a dry etching process using a gas mixture of SF 6 , H 2 , and CF 4 .
5. The method of claim 3 , wherein the selective etching process includes a wet etching process using NH 4 OH or TMAH.
6. The method of claim 1 , wherein the doping of the p-type dopant uses a doping energy ranging from 1 keV to 5 keV and a doping dose of the p-type dopant ranging from 1E15 cm −2 to 1E16 cm −2 .
7. The method of claim 1 , after the etching of the first and second dielectric layer and before the doping of the p-type dopant, further comprising:
depositing a third dielectric layer over the structure; and
performing an anisotropic etching process to the third dielectric layer to expose the first and second S/D features and to keep a portion of the third dielectric layer over sidewalls of the first and second gate structures.
8. The method of claim 1 , after the performing of the selective etching process, further comprising:
annealing the p-type dopant in the second S/D feature.
9. The method of claim 1 , before the performing of the selective etching process, further comprising:
annealing the p-type dopant in at least the second S/D feature.
10. The method of claim 1 , after the performing of the selective etching process, further comprising:
depositing a metal over remaining portions of the first and second S/D features.
11. The method of claim 10 , after the performing of the selective etching process and before the depositing of the metal, further comprising:
forming a first silicide feature over the remaining portion of the first S/D feature; and
forming a second silicide feature over the remaining portion of the second S/D feature.
12. A method of forming a semiconductor device, the method comprising:
providing a structure that includes:
a substrate;
a first gate structure and a second gate structure over the substrate;
a first source/drain (S/D) feature comprising n-type doped silicon adjacent to the first gate structure;
a second S/D feature comprising silicon germanium adjacent to the second gate structure; and
one or more dielectric layers over sidewalls of the first and second gate structures and over the first and second S/D features;
etching the one or more dielectric layers to expose the first and second S/D features;
doping a p-type dopant into the first and second S/D features by a same doping process, resulting in a p-type doped portion of the first S/D feature and a p-type doped portion of the second S/D feature; and
after the doping of the p-type dopant, partially etching the first and second S/D features by a same etching process, wherein the etching process recesses the first S/D feature at a faster rate than it recesses the second S/D feature.
13. The method of claim 12 , wherein the p-type dopant comprises boron and the doping process uses a doping energy ranging from 1 keV to 5 keV and a doping dose ranging from 1E15 cm −2 to 1E16 cm −2 .
14. The method of claim 12 , wherein the same etching process completely removes the p-type doped portion of the first S/D feature and partially removes the p-type doped portion of the second S/D feature.
15. The method of claim 12 , wherein the same etching process includes dry etching with a gas mixture of SF 6 , H 2 , and CF 4 .
16. The method of claim 12 , wherein the same etching process includes wet etching with NH 4 OH or TMAH.
17. The method of claim 12 , after the partially etching of the first and second S/D features, further comprising:
activating the p-type dopant in the second S/D feature.
18. The method of claim 17 , after the activating of the p-type dopant, further comprising:
cleaning a top surface of the first and second S/D features using a dry cleaning process or a wet cleaning process;
forming a first silicide feature over the first S/D feature; and
forming a second silicide feature the second S/D feature.
19. A method of forming a semiconductor device, the method comprising:
providing a structure that includes:
a substrate;
a first source/drain (S/D) feature comprising an n-type doped semiconductor material;
a second S/D feature comprising another semiconductor material different from the n-type doped semiconductor material; and
one or more dielectric layers over the first and second S/D features;
etching the one or more dielectric layers to expose the first and second S/D features;
doping a p-type dopant into the first and second S/D features; and
after the doping of the p-type dopant, recessing the first and second S/D features by a same etching process, wherein the same etching process completely removes a p-type doped portion of the first S/D feature and partially removes a p-type doped portion of the second S/D feature.
20. The method of claim 19 , after the recessing of the first and second S/D features, further comprising:
annealing the structure to at least activate the p-type dopant in the second S/D feature.