Self-referencing memory device
Self-referencing memory device, techniques, and methods are described herein. A self-referencing memory device may include a ferroelectric memory cell. The self-referencing memory device may be configured to determine a logic state stored in a memory cell based on a state signal generated using the ferroelectric memory cell and a reference signal generated using the ferroelectric memory cell. The biasing of the plate line of the ferroelectric memory cell may be used to generate the voltage need to generate the state signal during a first time period of an access operation and to generate the reference signal during a second time period of the access operation. Procedures and operations related to a self-referencing memory device are described.
1. An electronic memory apparatus, comprising:
a ferroelectric memory cell storing a charge and coupled with a digit line;
a state signal circuit selectively coupled with the digit line, the state signal circuit configured to extract at least a portion of the charge from the ferroelectric memory cell based on a first signal of the digit line; and
a reference signal circuit selectively coupled with the digit line, the reference signal circuit configured to generate a reference signal based at least in part on a second signal of the digit line different from the first signal, wherein the reference signal circuit further comprises a reference capacitor having a capacitor value that is at least twice a capacitor value of a charge capacitor of the state signal circuit.
2. The apparatus of claim 1 , further comprising:
a sense component having a first node and a second node, the first node coupled with a node of the state signal circuit and the second node coupled with a node of the reference signal circuit.
3. The apparatus of claim 1 , wherein the state signal circuit further comprises:
the charge capacitor to store the charge extracted from the ferroelectric memory cell; and
a p-mos cascode that selectively couples the charge capacitor to the digit line during an access operation.
4. The apparatus of claim 1 , wherein the reference signal circuit further comprises:
an n-mos cascode that selectively couples the reference capacitor to the digit line during an access operation.
5. The apparatus of claim 4 , wherein the reference signal circuit further comprises:
a switching component that selectively couples the reference capacitor to a reference node of a sense component or to a voltage source during the access operation.
6. The apparatus of claim 4 , wherein the reference signal circuit further comprises:
a switching component to selectively couple the reference capacitor to the n-mos cascode during the access operation.
7. The apparatus of claim 1 , further comprising:
a plate line driving circuit configured to bias a plate line to a plurality of voltages during an access operation.
8. The apparatus of claim 7 , wherein the plate line driving circuit further comprises:
a plurality of switching components to control a bias voltage of the plate line during the access operation.
9. A method, comprising:
receiving, by a state signal circuit coupled with a digit line, at least a portion of a charge stored on a ferroelectric capacitor based on a first signal on the digit line during a first time period of an access operation;
generating, by a reference signal circuit coupled with the digit line, a reference signal based on a second signal on the digit line during a second time period of the access operation after the first time period;
coupling a first node of a reference capacitor of the reference signal circuit to a reference node of a sense component using a first switching component after the reference signal circuit is isolated from the digit line during the access operation;
grounding a second node of the reference capacitor using a second switching component after the reference signal circuit is isolated from the digit line during the access operation; and
determining a logic state of the ferroelectric capacitor based at least in part on a state signal indicative of the charge received by the state signal circuit and the reference signal, coupling the first node of the reference capacitor to the reference node, and grounding the second node of the reference capacitor.
10. The method of claim 9 , further comprising:
coupling the state signal circuit to the digit line during the first time period by activating a cascode.
11. The method of claim 9 , further comprising:
biasing a plate line coupled with the ferroelectric capacitor to a first voltage level greater than a voltage level of the digit line during the first time period, wherein the first signal on the digit line is based at least in part on biasing the plate line.
12. The method of claim 11 , further comprising:
isolating the state signal circuit from the digit line before generating the reference signal.
13. The method of claim 9 , further comprising:
biasing a plate line coupled with the ferroelectric capacitor to a second voltage level less than a voltage level of the digit line during the second time period, wherein the second signal on the digit line is based at least in part on biasing the plate line.
14. The method of claim 9 , further comprising:
coupling the reference signal circuit to the digit line during the second time period by activating a cascode.
15. The method of claim 9 , further comprising:
isolating the reference signal circuit from the digit line by de-activating a cascode.
16. The method of claim 9 , further comprising:
activating the sense component to compare the state signal indicative of the charge received by the state signal circuit and the reference signal, wherein determining the logic state is based at least in part on the comparison.
17. The method of claim 9 , further comprising:
coupling the ferroelectric capacitor to the digit line during the access operation, wherein the first time period and the second time period occur while the ferroelectric capacitor is coupled with the digit line.