Methods of memory address verification and memory devices employing the same
A memory device and methods for operating the same are provided. The memory device includes an array of memory cells, a non-volatile memory, and a controller. The controller is configured to receive a read command to read a data word from an address of the array and decode the address to generate a decoded address. The controller is further configured to retrieve response data from the decoded address of the array, retrieve a location indicia corresponding to the decoded address from the non-volatile memory, and verify that the location indicia corresponds to the address. The controller can optionally be further configured to indicate an error if the location indicia does not correspond to the address.
1. A memory device, comprising:
an array of memory cells;
a non-volatile memory; and
a controller configured to:
receive a read command to read a data word from a logical address of the array,
decode the logical address to generate a physical address,
retrieve response data directly from a first location in the array, the first location addressed at the physical address of the array,
retrieve a location indicia from a second location in the non-volatile memory, the second location addressed at the physical address of the non-volatile memory, and
verify that generating the physical address was performed without error by comparing the location indicia to the logical address.
2. The memory device of claim 1 , wherein the controller is further configured to indicate an error if the location indicia does not correspond to the logical address.
3. The memory device of claim 1 , wherein the controller is further configured to output the data word if the location indicia corresponds to the logical address.
4. The memory device of claim 1 , wherein the controller is further configured to generate a plurality of location indicia including the location indicia and store the plurality of location indicia in the non-volatile memory.
5. The memory device of claim 4 , wherein each of the plurality of location indicia correspond to a single one of a corresponding plurality of logical addresses of the array.
6. The memory device of claim 1 , wherein the location indicia is a hash of the logical address.
7. The memory device of claim 1 , wherein the location indicia is the logical address.
8. The memory device of claim 1 , wherein the array of memory cells is a volatile array.
9. The memory device of claim 1 , wherein the non-volatile memory is operated at a different voltage than the array.
10. The memory device of claim 1 , wherein the memory device is a semiconductor die, and wherein the controller is an on-die controller.
11. The memory device of claim 1 , wherein the memory device is a memory module, and wherein the controller is on a semiconductor die and the array of memory cells is on a second semiconductor die.
12. The memory device of claim 1 , wherein the controller is further configured to:
enable or disable:
retrieving the location indicia from the second location in the non-volatile memory, and
verifying that generating the physical address was performed without error by comparing the location indicia to the logical address.
13. A method of operating a memory device including an array of memory cells and a non-volatile memory, the method comprising:
receiving a read command to read a data word from a logical address of the array;
decoding the logical address to generate a physical address,
retrieving response data directly from a first location in the array, the first location addressed at the physical address of the array;
retrieving a location indicia from a second location in the non-volatile memory, the second location addressed at the physical address of the non-volatile memory; and
verifying that generating the physical address was performed without error by comparing the location indicia to the logical address.
14. The method of claim 13 , further comprising indicating an error if the location indicia does not correspond to the physical logical address.
15. The method of claim 13 , further comprising outputting the data word if the location indicia corresponds to the logical address.
16. The method of claim 13 , further comprising generating a plurality of location indicia including the location indicia and storing the plurality of location indicia in the non-volatile memory.
17. The method of claim 16 , wherein each of the plurality of location indicia correspond to a single one of a corresponding plurality of logical addresses of the array.
18. The method of claim 13 , wherein the location indicia is a hash of the logical address.
19. The method of claim 13 , wherein the location indicia is the logical address.
20. The method of claim 13 , wherein the array of memory cells is a volatile array.
21. The method of claim 13 , wherein the non-volatile memory is operated at a different voltage than the array.
22. The method of claim 13 , further comprising disabling the retrieving the location indicia and the verifying that the location indicia corresponds to the logical address.
23. A memory device, comprising:
an array of memory cells;
a non-volatile memory; and
a controller configured to:
receive a write command to write a data word to a logical address of the array,
decode the logical address to generate a physical address,
write the data word directly to a first location in the array, the first location addressed at the physical address of the array,
retrieve a location indicia from a second location in the non-volatile memory, the second location addressed at the physical address of the non-volatile memory, and
verify that generating the physical address was performed without error by comparing the location indicia to the logical address.
24. The memory device of claim 23 , wherein the controller is further configured to write the data word to the first location in the array in response to verifying that the location indicia corresponds to the logical address.