Decode circuitry coupled to a memory array
In an example, an apparatus includes a memory array in a first region and decode circuitry in a second region separate from a semiconductor. The decode circuitry is coupled to an access line in the memory array.
1. An apparatus, comprising:
a memory array in a first region; and
decode circuitry in a second region separate from a semiconductor wherein:
the decode circuitry is coupled to an access line in the memory array; and
the decode circuitry comprises a trigger device located between the access line and a switch device and the switch device located between a global decode node and the trigger device, the switch device operating separate from a select device below the access line and the trigger device to cause a threshold current to flow through the switch device.
2. The apparatus of claim 1 , wherein the access line is a first access line and wherein the memory array comprises a memory cell between and coupled to the first access line and a second access line.
3. The apparatus of claim 2 , wherein the memory cell comprises a resistive element.
4. The apparatus of claim 3 , wherein the resistive element comprises a variable resistance material.
5. The apparatus of claim 2 , wherein the memory cell is a first memory cell, and further comprising a second memory cell between and coupled to the first access line and a third access line, wherein the first access line is between the first and second memory cells.
6. The apparatus of claim 5 , wherein the memory array is a three-dimensional cross-point memory array.
7. The apparatus of claim 5 , wherein the second and third access lines are each coupled to the decode circuitry on and/or in a semiconductor in a third region.
8. The apparatus of claim 1 , wherein the second region is in a backend region of the apparatus.
9. The apparatus of claim 1 , further comprising a global decode node coupled to the decode circuitry.
10. The apparatus of claim 1 , wherein the memory array comprises self-selecting memory cells.
11. The apparatus of claim 1 , further comprising an additional memory array in a third region over the second region and additional decode circuitry in a fourth region over the second region, wherein the additional decode circuitry is coupled to the additional memory array.
12. The apparatus of claim 1 , further comprising a metal region between the semiconductor and the decoder.