Scalable, parameterizable, and script-generatable buffer manager architecture
A buffer manager is generated by executing a script with respect to a buffer architecture template and a configuration file specifying parameters for the buffer such as, for example, number of memory banks, width of memory banks, depth of memory banks, and client bridge FIFO depth. The script converts the buffer architecture template into a hardware description language (HDL) description of a buffer manager having the parameters. Client bridges accumulate requests for memory banks in FIFO that is provided to a buffer manager upon the client bridge being granted arbitration. Accesses of memory banks may be performed one at a time in consecutive clock cycles in a pipelined manner. Client bridges and the buffer manager may operate in different clock domains. The clock frequency of the buffer manager may be increased or decreased according to requests from client devices.
1. A method for generating a buffer specification comprising:
receiving, by a computer system, a buffer template defining a buffer manager architecture;
receiving, by the computer system, a configuration file defining at least one of a number of memory banks, a memory bank width, a number of clients, and a client buffer depth;
executing, by the computer system, a script with respect to the buffer template and configuration file, the script outputting a hardware description language (HDL) file defining instructions for generating a buffer; and
outputting, via a clock rate manager, a bandwidth signal for each client bridge of the plurality of client bridges, wherein the clock rate manger includes a masking stage configured to output a bandwidth signal for each client bridge of the plurality of client bridges.
2. The method of claim 1 , wherein the buffer manager architecture includes HDL code defining:
a memory bank manager configured to receive requests and arbitrate and execute requests with respect to a plurality of memory banks; and
a client bridge definition, defining an input, an accumulation register configured to store requests from the input, and a client bridge state controller programmed to receive an arbitration assignment from the memory bank manager, and, in response to receiving the arbitration assignment, output requests stored in the accumulation register to the memory bank manager.
3. The method of claim 2 , wherein:
the configuration file includes the number of clients; and
executing the script with respect to the buffer template and configuration file comprises including in the HDL file instructions for generating a plurality of client bridges having the client bridge definition, the plurality of client bridges corresponding to the number of clients in the configuration file.
4. The method of claim 2 , wherein the method further comprises:
performing, via the memory bank manager, pipelined access of a plurality of memory banks for each request received from the client bridge whereby an address included in the request is accessed consecutively, from one memory bank of the plurality of memory banks per clock cycle until the address is accessed for each memory bank of the plurality of memory banks.
5. The method of claim 4 , wherein the method further comprises:
performing, via the memory bank manager, arbitration assignment among a plurality of client bridges according to a round robin algorithm.
6. The method of claim 4 , wherein the method further comprises:
initiating, via the memory bank manager, pipelined access of a plurality of memory banks once per clock cycle such that multiple pipelined accesses of the plurality of memory banks are performed simultaneously.
7. The method of claim 4 , wherein the method further comprises:
configuring the memory bank manager to belong to a first clock domain; and
configuring a plurality of client bridges to belong to one or more second clock domains different from the first clock domain.
8. The method of claim 1 , wherein the clock rate manager is configured to increase a frequency of a first clock domain in response to a first loading of the plurality of memory banks and decrease the frequency of the first clock domain in response to a second loading of the plurality of memory banks, the second loading being less than the first loading.
9. The method of claim 1 , wherein the clock rate manager includes a block rate selection stage that selects the frequency of the first clock domain according to the bandwidth signals from the masking stage.
10. The method claim 1 , wherein the buffer has the buffer manager architecture configured to have the at least one of the number of memory banks, the memory bank width, the number of clients, and the client buffer depth of the configuration file.
11. The method of claim 1 , wherein the configuration file defines all of the number of memory banks, the memory bank width, the number of clients, and the client buffer depth.
12. A buffer comprising:
a memory bank manager configured to receive requests from a plurality of clients and arbitrate and execute requests with respect to a plurality of memory banks;
a plurality of client bridges, each client bridge defining an input, an accumulation register configured to store requests from the input, and a client bridge state controller programmed to receive an arbitration assignment from the memory bank manager; and
a clock rate manager configured to output a bandwidth signal for each client bridge of the plurality of client bridges, wherein the clock rate manger includes:
a block rate selection stage to select the frequency of the first clock domain according to a bandwidth signal for each client bridge of the plurality of client bridges.
13. The buffer of claim 12 , wherein the memory bank manager is further configured to perform, for each request received from the client bridge, a pipelined access of the plurality of memory banks whereby an address included in the request is accessed consecutively, from one memory bank of the plurality of memory banks per clock cycle until the address is accessed for each memory bank of the plurality of memory banks.
14. The buffer of claim 12 , wherein the memory bank manager is further configured to:
perform arbitration assignment among the plurality of client bridges according to a round robin algorithm.
15. The buffer of claim 12 , wherein the memory bank manager is further configured to:
initiate pipelined access of the plurality of memory banks once per clock cycle such that multiple pipelined accesses of the plurality of memory banks are performed simultaneously.
16. The buffer of claim 12 , wherein the memory bank manager is further configured to:
belong to a first clock domain; and
the plurality of client bridges are configured to belong to one or more second clock domains different from the first clock domain.
17. The buffer of claim 12 , wherein the clock rate manager is configured to increase a frequency of the first clock domain in response to a first loading of the plurality of memory banks and decrease the frequency of the first clock domain in response to a second loading of the plurality of memory banks, the second loading being less than the first loading.
18. The buffer of claim 12 , wherein the clock rate manager includes:
a masking stage configured to output the bandwidth signal for each client bridge of the plurality of client bridges, the bandwidth signal for each client bridge of the plurality of client bridges that is currently processing requests being a bandwidth requirement for the each client bridge, the bandwidth signal for each client bridge of the plurality of client bridges that is not currently processing requests being zero.
19. A method for generating a buffer specification comprising:
receiving, by a computer system, a buffer template defining a buffer manager architecture;
receiving, by the computer system, a configuration file defining at least one of a number of memory banks, a memory bank width, a number of clients, and a client buffer depth;
outputting, by the computer system, a hardware description language (HDL) file defining instructions for generating a buffer;
mapping, via a memory bank manager, an external slot address to a plurality of micro-slot addresses corresponding to a plurality of physical locations within the at least one of the number of memory banks; and
translating, via the memory bank manager, requests referencing the external slot address to the plurality of micro-slot addresses.
20. The method of claim 19 , wherein the buffer manager architecture includes HDL code defining instructions for generating a buffer having the buffer manager architecture configured to have the at least one of the number of memory banks, the memory bank width, the number of clients, and the client buffer depth of the configuration file.