Fill fins for semiconductor devices
A semiconductor device includes a semiconductor substrate, first and second device fins extending from the semiconductor substrate, and a fill fin disposed on the semiconductor substrate and between the first and second device fins, wherein the fill fin has an opening. The semiconductor device further includes a first gate structure extending continuously from a channel region of the first device fin to a channel region of the second device fin through the opening.
1. A semiconductor device, comprising:
a semiconductor substrate;
first and second device fins extending upwardly from the semiconductor substrate, each of the first and second device fins extending lengthwise in a first direction;
a fill fin disposed on the semiconductor substrate and between the first and second device fins, the fill fin including a dielectric material extending continuously along the first direction throughout the fill fin, wherein the fill fin has a notch; and
a first gate structure extending continuously from a channel region of the first device fin to a channel region of the second device fin through the notch.
2. The semiconductor device of claim 1 , further comprising:
a dielectric material layer disposed between the first and second device fins and between the fill fin and the semiconductor substrate.
3. The semiconductor device of claim 2 , wherein the dielectric material layer is a shallow trench isolation (STI) feature.
4. The semiconductor device of claim 1 , further comprising:
a second gate structure over the first device fin; and
a third gate structure over the second device fin, wherein the second gate structure is electrically isolated from the third gate structure by the fill fin.
5. The semiconductor device of claim 1 , wherein:
a top surface of the fill fin outside the notch is above top surfaces of the first and second device fins; and
a bottom surface of the fill fin is above bottom surfaces of the first and second device fins.
6. The semiconductor device of claim 5 , wherein the top surface of the fill fin in the notch is below the top surfaces of the first and second device fins.
7. The semiconductor device of claim 1 , wherein the fill fin includes metal oxide.
8. The semiconductor device of claim 1 , wherein the first gate structure fills up the notch.
9. The semiconductor device of claim 1 , wherein the notch is disposed in a topmost portion of the fill fin.
10. The semiconductor device of claim 9 , wherein the notch has a vertical depth in a range from about 15 nm to about 40 nm.
11. A device, comprising:
a device fin extending from a substrate;
a dielectric fin disposed above the substrate, a top portion of the dielectric fin having a notch;
an isolation feature disposed on sidewalls of both the device fin and the dielectric fin, wherein a portion of the isolation feature is directly under a bottommost portion of the dielectric fin; and
a gate structure engaging a top portion of the device fin and extending through the notch.
12. The device of claim 11 , wherein a bottom surface of the dielectric fin is between a top surface and a bottom surface of the isolation feature.
13. The device of claim 11 , wherein a bottom surface of the dielectric fin is higher than a bottom surface of the device fin.
14. The device of claim 11 , wherein:
a top surface of the dielectric fin outside the notch is higher than a top surface of the device fin; and
the top surface of the dielectric fin inside the notch is lower than the top surface of the device fin.
15. The device of claim 11 , wherein the gate structure includes an input/output (I/O) oxide layer on a sidewall of the dielectric fin and is free of the I/O oxide layer on a top surface of the dielectric fin inside the notch.
16. The device of claim 11 , wherein the device fin and the dielectric fin have substantially the same horizontal width.
17. A semiconductor device, comprising:
a substrate;
an isolation feature above the substrate;
a device fin extending from the substrate and through the isolation feature;
first and second fill fins disposed above the isolation feature and sandwiching the device fin, wherein the first fill fin has a trench above the isolation feature, wherein a bottom surface of the first fill fin is above a bottom surface of the second fill fin; and
a gate stack over a channel region of the device fin, wherein a portion of the gate stack fills the trench.
18. The semiconductor device of claim 17 , wherein a top surface of the first fill fin outside the trench is above a top surface of the device fin.
19. The semiconductor device of claim 17 , wherein a top surface of the device fin is between a top surface of the first fill fin in the trench and a top surface of the second fill fin.
20. The semiconductor device of claim 1 , wherein the fill fin has a first sidewall, a second sidewall opposing the first sidewall, and a top surface in the notch extending from the first sidewall to the second sidewall, further comprising:
a dielectric layer disposed on at least one of the first and second sidewalls without extending to the top surface.