IP Library Granted Patent US 11,188,234
Granted Patent B2
US 11,188,234 · App. 15/690,503 · Granted Nov 30, 2021

Cache line data

Inventors: Cagdas Dirik (Indianola, WA); Robert M. Walker (Raleigh, NC)
Assignee: Micron Technology, Inc.
G06F3/0611G06F3/0659G06F3/0685G06F12/0806G06F12/0868G06F12/0879G06F12/128G06F12/0862G06F12/0882G06F2212/1021G06F2212/313G06F2212/604G06F2212/6028G06F2212/621
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 11,188,234
App. No.
15/690,503
Granted
Nov 30, 2021
Kind
B2
Abstract

The present disclosure includes apparatuses and methods related to a memory system with cache line data. An example apparatus can store data in a number of cache lines in the cache, wherein each of the number of lines includes a number of chunks of data that are individually accessible.

Claims (80)

1. An apparatus, comprising:

a cache controller; and

a cache and a memory device coupled to the cache controller, wherein the cache controller is configured to issue commands to cause the cache to:

store data in a number of cache lines in the cache, wherein:

each of the number of cache lines includes a number of chunks of data that are individually accessible;

in response to a request from the cache controller resulting in a hit, wherein the hit includes a portion of the number of chunks of data on a first cache line of the number of cache lines:

read the portion of the number of chunks of data stored in the first cache line of the number of cache lines and return the portion of the number of chunks of data to the cache controller, wherein:

the portion of the number of chunks of data is less than a total number of chunks of data on the first cache line of the number of cache lines;

prioritize particular chunks of data that will not be evicted from the cache lines, wherein a host identifies chunks of data in the cache that are never evicted from the cache;

select dirty chunks of the first cache line for writing back to the memory device, wherein the selected dirty chunks include chunks of the portion of the number of chunks that were a hit and returned to the cache controller when executing the request and wherein the selected dirty chunks remain valid in the first cache line that included chunks that were a hit.

2. The apparatus of claim 1 , wherein each of the number of lines includes metadata, chunk metadata, tag information, and the number of chunks of data.

3. The apparatus of claim 1 , wherein the cache controller is configured to cause the cache to access a portion of the number of chunks of data in a particular cache entry while executing a command.

4. The apparatus of claim 1 , wherein each of the number of lines includes metadata that is managed using a buffer on the cache controller.

5. The apparatus of claim 1 , wherein each of the number of lines includes chunk metadata that is managed and updated by the cache controller as commands are executed.

6. An apparatus, comprising:

a cache controller; and

a cache and a memory device coupled to the cache controller, wherein the cache controller is configured to issue commands to cause the cache to:

access a portion of a number of chunks of data in a first cache line of a number of cache lines of the cache in response to receiving a request, wherein:

the cache controller manages the request using a buffer on the cache controller; and

the cache controller services the request by:

reading the portion of the number of chunks of data from the first cache line of the number of cache lines in response to the request resulting in a hit, wherein:

 the portion of the number chunks of data corresponding to the hit are the portion of the number of chunks of data from the cache lines; and

 the portion of the number of chunks of data is less than a total number of chunks of data; and

returning the portion of the number of chunks of data in the first cache line corresponding to the hit;

in response to determining the request is a hit, pre-fetch chunks of data and write the number of chunks of data to the cache line, wherein the pre-fetched chunks of data were not included in the request and are located in a portion of the memory device where the portion of the number of chunks of data returned when servicing the request are located such that the number of chunks of data returned when the servicing the request and the pre-fetched chunks of data are on the same cache line;

prioritize particular chunks of data that will remain in the cache lines, wherein:

the particular chunks of data are prioritized based on the frequency at which the chunks of data will be accessed; and

a host identifies chunks of data that will never be evicted from the cache; and

select dirty chunks of the first cache line for writing back to the memory device, wherein the selected dirty chunks include chunks of the portion of the number of chunks that were a hit and returned to the cache controller when executing the request and wherein the selected dirty chunks remain valid in the first cache line that included chunks that were a hit.

7. The apparatus of claim 6 , wherein the cache controller is configured to issue commands to cause the cache to return the portion of the number of chunks of data corresponding to the request that were in the cache line when the request was received in response to cache controller determining the request is a hit.

8. The apparatus of claim 6 , wherein the cache controller is configured to issue commands to cause the cache to retrieve the portion of the number of chunks of data corresponding to the request from the memory device in response to cache controller determining the request is a miss.

9. The apparatus of claim 6 , wherein the cache controller is configured to issue commands to cause the cache to, in response to determining the request is a miss, write dirty chunks of data in the cache line to the memory device that were in the cache line when the request was received.

10. The apparatus of claim 6 , wherein the cache controller is configured to issue commands to cause the cache to, in response to determining the request is a miss, select the cache line based upon the cache line having fewer dirty chunks than other cache lines in the cache.

11. The apparatus of claim 6 , wherein the cache controller is configured to issue commands to cause the cache to, in response to determining the request is a hit, write dirty chunks of data in the cache line to the memory device.

12. The apparatus of claim 6 , wherein the cache controller is configured to issue commands to cause the cache to, in response to determining the request is a hit, replace chunks of data in the cache line that are not associated with the request and were invalid when the request was received.

13. An apparatus, comprising:

a cache controller; and

a cache and a memory device coupled to the cache controller, wherein the cache controller is configured to:

receive requests from a host;

manage the requests using a buffer on the cache controller;

service commands by:

returning a portion of a number of chunks of data from a first cache line of a number of cache lines of the cache to the host, in response to the request resulting in a hit, wherein:

the portion of the number of chunks of data correspond to the hit;

reading the portion of the number of chunks of data from the cache lines, wherein:

the portion of the number of chunks of data is less than a total number of chunks of data;

the host identifies chunks of the data in the cache that are never evicted from the cache; and

the dirty chunks remain valid in the cache line that included chunks that were a hit; and

prioritize particular chunks of data that will not be evicted from the cache lines, wherein:

the particular chunks of data are prioritized based on a type of data.

14. The apparatus of claim 13 , wherein the cache controller is configured to write the chunks of data from the memory device to the cache prior to receiving a request for the chunks of data.

15. The apparatus of claim 13 , wherein the cache controller is configured to write dirty chunks of data to the memory device when not servicing commands.

16. The apparatus of claim 13 , wherein the cache controller is configured to select chunks of data to remain in the cache based on a command from the host.

17. A method, comprising:

receiving a request for data at a cache controller;

determining whether portions of a number of chunks of data associated with the request are in the cache using a buffer on the cache controller;

servicing the request, in response to determining the request resulted in a hit, by:

reading the portion of the number of chunks of data that correspond to the hit from a first cache line of a number of cache lines, wherein:

the portion of the number of chunks of data is less than a total number of chunks of data;

returning the portion of the number of chunks of data corresponding to the hit from the first cache line indicated by the buffer;

in response to determining the request is a hit, pre-fetching chunks of data and writing the chunks to the cache line, wherein the pre-fetched chunks of data were not included in the request and are located in a portion of a memory device where the portion of the number of chunks of data returned when servicing the request are located;

prioritizing particular chunks of data that will not be evicted from the cache lines, wherein the host identifies chunks of the data in the cache that are never evicted from the cache and wherein the chunks of data are prioritized based on:

the frequency at which the data will be accessed; and

the type of data; and

selecting dirty chunks of the first cache line for writing back to the memory device, wherein the selected dirty chunks include chunks of the portion of the number of chunks that were a hit and returned to the cache controller when executing the request and wherein the selected dirty chunks remain valid in the first cache line that included chunks that were a hit.

18. The method of claim 17 , further including servicing the request, in response to determining the request is a miss, by writing a number of chunks of data associated with the request from a memory device to a cache line indicated by the buffer.

19. The method of claim 18 , further including servicing the request, in response to determining the request is a miss, by returning a number of chunks of data from the cache line indicated by the buffer.

20. The method of claim 17 , wherein servicing the request includes updating chunk metadata associated with the number of chunks of data.

21. A method, comprising:

storing data in a number of cache lines in the cache, wherein:

each of the number of cache lines includes a number of chunks of data that are individually accessible by a cache controller;

reading a portion of the number of chunks of data from a first cache line of the number of cache lines in response to a request resulting in a hit, wherein:

the portion of the number of chunks of data correspond to the hit; and

the portion of the number of chunks of data is less than a total number of chunks of data;

pre-fetching a number of chunks of data to replace chunks of data on a particular cache line that were not associated with a request that resulted in a hit and were invalid when the request was received, wherein the request resulted in a hit on the particular cache line;

prioritizing, in response to determining the request is a hit, particular chunks of data that will remain in the cache lines, wherein a host identifies portions of data in the cache that are never evicted from the cache; and

selecting dirty chunks of the first cache line for writing back to the memory device, wherein the selected dirty chunks include chunks of the portion of the number of chunks that were a hit and returned to the cache controller when executing the request and wherein the selected dirty chunks remain valid in the first cache line that included chunks that were a hit.

22. The apparatus of claim 1 , further including servicing a request for data using data stored in a buffer on the cache controller.

23. The apparatus of claim 1 , further including accessing a portion of the number of chunks of data in a particular cache entry while executing a command.

24. The apparatus of claim 1 , further including managing the data in the cache using a buffer on the cache controller.

25. The apparatus of claim 1 , wherein further including managing chunk metadata by the cache controller as commands are executed.

Assignments (7)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050709/0838 →
RELEASE OF SECURITY INTEREST Recorded Jul 20, 2018
From: U.S. BANK NATIONAL ASSOCIATION, AS AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 046597/0333 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
SUPPLEMENT NO. 6 TO PATENT SECURITY AGREEMENT Recorded Nov 1, 2017
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 044348/0253 →
SUPPLEMENT NO. 6 TO PATENT SECURITY AGREEMENT Recorded Nov 1, 2017
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 044653/0333 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 30, 2017
From: DIRIK, CAGDAS; WALKER, ROBERT M.
To: MICRON TECHNOLOGY, INC.
Reel/Frame 043446/0255 →
Continuity (1)
Related Publication 20190065072A1 · Feb 28, 2019