Integrated circuit design and/or fabrication
A computer-implemented method of generating a layout of a circuit block of an integrated circuit comprises: receiving input data defining a logical operation of the circuit block; accessing a cell library providing a plurality of candidate cells; determining, with reference to the input data, a set of cells to be used to implement the circuit block, the cells defining circuit elements for fabrication on a substrate; and generating the layout by employing a place and route tool to determine a placement of the set of cells and performing a routing operation to interconnect interface terminals of the set of cells by determining routing paths to be provided within a plurality of metal layers including a lowest metal layer overlying the cells and within which interface terminals of the cells are provided and one or more further metal layers overlying the lowest metal layer; in which the step of determining routing paths comprises determining a routing path between interface terminals of a group of two or more cells by providing, in the generated layout, (i) an interconnection overlying the interface terminals of the group of two or more cells in one of the one or more further metal layers and (ii) via connections between the interconnection and the interface terminals of the group of two or more cells.
1. A computer-implemented method of generating a layout of a circuit block of an integrated circuit, comprising:
receiving input data defining a logical operation of the circuit block;
accessing a cell library providing a plurality of candidate cells;
determining, with reference to the input data, a set of cells to be used to implement the circuit block, the cells defining circuit elements for fabrication on a substrate; and
generating the layout by employing a place and route tool to determine a placement of the set of cells and performing a routing operation to interconnect interface terminals of the set of cells by determining routing paths to be provided within a plurality of metal layers including a lowest metal layer overlying the cells and within which interface terminals of the cells are provided and one or more further metal layers overlying the lowest metal layer;
in which:
the step of determining routing paths comprises determining a routing path between interface terminals of a group of two or more cells by providing, in the generated layout, (i) an interconnection overlying the interface terminals of the group of two or more cells in one of the one or more further metal layers and (ii) via connections between the interconnection and the interface terminals of the group of two or more cells;
the interface terminals in the lowest metal layer are elongate regions subject to a design constraint imposing a minimum separation of a via connection from an end of one of the elongate regions;
interconnections within the second-lowest metal layer are elongate regions;
the elongate regions in the first metal layer and the second-lowest metal layer are in orthogonal directions; and
the providing step comprises providing a via connection offset from a central longitudinal axis of an interconnection in the second-lowest metal layer so as not to violate the design constraint.
2. A method according to claim 1 , in which the providing step comprises providing at least a part of the interconnection in a second-lowest metal layer overlying the lowest metal layer.
3. A method according to claim 2 , in which the providing step comprises providing at least a part of the interconnection in another of the further metal layers overlying the second-lowest metal layer.
4. A method according to claim 1 , in which:
the interface terminals comprise input terminals and output terminals; and
for the group of two or more cells, the routing path is between at least one input terminal and at least one output terminal.
5. A method according to claim 1 , in which the plurality of candidate cells comprises one or more groups of electrically equivalent candidate cells in which, for a group of electrically equivalent cells, the circuit functionality is the same but the layout of interface terminals differs between the electrically equivalent cells.
6. A method according to claim 5 , in which the step of determining a set of cells comprises selecting, for a given cell having a required cell functionality, one of a group of electrically equivalent cells providing that required cell functionality taking into account the routing of a routing path between interface terminals of the given cell and one or more other cells.
7. A method as claimed in claim 1 , in which the lowest metal layer is a metal 0 (M0) layer.
8. A method as claimed in claim 1 , further comprising the steps of:
incorporating the layout of the circuit block within a layout of an integrated circuit; and
manufacturing the integrated circuit from the layout of the integrated circuit.
9. An integrated circuit manufactured according to the method of claim 8 .
10. A computer program product on a non-transitory storage medium for controlling a computer to perform a method of generating a layout of a circuit block as claimed in claim 1 .
11. A computer-implemented method of generating a layout of a circuit block of an integrated circuit, comprising:
receiving input data defining a logical operation of the circuit block;
accessing a cell library providing a plurality of candidate cells;
determining, with reference to the input data, a set of cells to be used to implement the circuit block, the cells defining circuit elements for fabrication on a substrate; and
generating the layout by employing a place and route tool to determine a placement of the set of cells and performing a routing operation to interconnect interface terminals of the set of cells by determining routing paths to be provided within a plurality of metal layers including a lowest metal layer overlying the cells and within which interface terminals of the cells are provided and one or more further metal layers overlying the lowest metal layer;
in which:
the step of determining routing paths comprises determining a routing path between interface terminals of a group of two or more cells by providing, in the generated layout, an interconnection between the interface terminals within the lowest metal layer; and
the interface terminals in the lowest metal layer are elongate regions in a predetermined orientation.
12. A method according to claim 11 , in which the interconnection comprises an elongate region in the lowest metal layer between an interface terminal at a lateral edge, with respect to the predetermined orientation, of a cell and an interface terminal at a lateral edge of a next-adjacent cell.
13. A method according to claim 11 , in which:
the plurality of candidate cells comprises at last one filler cell providing cell spacing and at least power rail continuity, the filler cell defining elongate filler regions in the lowest metal layer in the predetermined orientation;
in which the step of determining routing paths comprises providing, in the generated layout, an interconnection within the lowest metal layer between the interface terminals and one or more elongate filler region of an intervening filler cell.
14. A method according to claim 13 , in which, for a routing path between interface terminals of a pair of cells, the step of determining routing paths comprises:
providing, in the generated layout, an interconnection within the lowest metal layer between an interface terminal of one of the pair of cells and a first one of the one or more elongate filler region of an intervening filler cell within the lowest metal layer;
providing, in the generated layout, an interconnection within the lowest metal layer between an interface terminal of the other of the pair of cells and a second, different, one of the one or more elongate filler region of the intervening filler cell within the lowest metal layer; and
providing, in the generated layout, an interconnection within another metal layer other than the lowest metal layer between the first and second elongate filler regions.
15. A method according to claim 11 , in which:
the interface terminals comprise input terminals and output terminals; and
for the group of two or more cells, the routing path is between at least one input terminal and at least one output terminal.
16. A method according to claim 11 , in which:
the step of determining routing paths comprises determining a routing path between interface terminals of a group of two or more cells by providing, in the generated layout, (i) an interconnection overlying an interface terminal of the group of two or more cells in one of the one or more further metal layers (ii) a via connection between the interconnection and the interface terminals of the group of two or more cells; and (iii) one or more inhibited regions spatially separated from the interconnection in which the routing of connections to the interface terminal is inhibited.
17. A method as claimed in claim 11 , in which the lowest metal layer is a metal 0 (M0) layer.
18. A method according to claim 11 , in which the plurality of candidate cells comprises one or more groups of electrically equivalent candidate cells in which, for a group of electrically equivalent cells, the circuit functionality is the same but the layout of interface terminals differs between the electrically equivalent cells.
19. A method according to claim 18 , in which the step of determining a set of cells comprises selecting, for a given cell having a required cell functionality, one of a group of electrically equivalent cells providing that required cell functionality taking into account the routing of a routing path between interface terminals of the given cell and one or more other cells.
20. A method as claimed in claim 11 , further comprising the steps of:
incorporating the layout of the circuit block within a layout of an integrated circuit; and
manufacturing the integrated circuit from the layout of the integrated circuit.
21. An integrated circuit manufactured according to the method of claim 20 .
22. A computer program product on a non-transitory storage medium for controlling a computer to perform a method of generating a layout of a circuit block as claimed in claim 11 .