System on chip module configured for event-driven architecture
A system on chip (SoC) module is described herein, wherein the SoC modules comprise a processor subsystem and a hardware logic subsystem. The processor subsystem and hardware logic subsystem are in communication with one another, and transmit event messages between one another. The processor subsystem executes software actors, while the hardware logic subsystem includes hardware actors, the software actors and hardware actors conform to an event-driven architecture, such that the software actors receive and generate event messages and the hardware actors receive and generate event messages.
1. A method performed on a System on Chip (SoC) module that comprises a processor subsystem and field programmable gate array (FPGA) fabric in communication with one another, the method comprising:
detecting, by way of an event broker component that is executed by a processor of the processor subsystem, receipt of a first event message at the processor subsystem
directing the first event message to the processor of the processor subsystem by way of the event broker component;
executing, at the processor, an event-driven process responsive to the processor receiving the first event message, the event-driven process configured to cause the processor to generate a first output event message responsive to the processor executing the process;
detecting, by way of event broker logic of the FPGA fabric, receipt of a second event message at the FPGA fabric;
directing the second event message to an event-driven hardware logic module of the FPGA fabric; and
triggering the event-driven hardware logic module responsive to receiving an indication that the second event message is directed to the event-driven hardware logic module, the event-driven hardware logic module configured to generate a second output event message responsive to being triggered.
2. The method of claim 1 , wherein directing the first event message to the processor comprises directing the first event message to both the processor and the hardware logic module.
3. The method of claim 2 , wherein the event-driven process and the event-driven hardware logic module are configured to perform the same function.
4. The method of claim 1 , wherein the directing of the second event message is performed by the processor of the processor subsystem.
5. The method of claim 1 , the method further comprising:
directing the first output event message to the event-driven hardware logic module; and
triggering the event-driven hardware logic module responsive to receiving an indication that the first output event message is directed to the event-driven hardware logic module.
6. The method of claim 1 , wherein the directing of at least one of the first event message or the second event message is performed by the event broker logic of the FPGA fabric.