Boosting channels of memory cells
A method for programming a non-volatile memory device includes concurrently boosting channels of memory cells in a selected memory string and an unselected memory string of the memory device, discharging the boosted channels of the memory cells in the selected memory string, and programming a selected memory cell in the selected memory string after discharging the boosted channels in the selected memory string.
1. A method of programming memory cells of a non-volatile NAND architecture memory array, comprising:
applying a first bias voltage to a control gate of select transistors in selected and unselected NAND architecture memory strings, wherein the first bias voltage maintains the select transistors in an off state;
applying a pass voltage to access lines of memory cells in the selected and unselected memory strings while the select transistors are in the off state to boost channels of the memory cells in the selected and unselected memory strings;
discharging the boosted channels of the memory cells in the selected memory strings; and
programming selected memory cells in the selected memory strings after discharging the boosted channels in the selected memory strings.
2. The method of claim 1 , wherein discharging the boosted channels comprises:
applying a second bias voltage to the control gates of the select transistors in the selected and unselected memory strings, wherein the second bias voltage causes the select transistors in the selected memory strings to enter an on state to discharge the boosted channels in the selected memory strings.
3. The method of claim 2 , wherein the second bias voltage maintains the select transistors in the unselected memory strings in the off state to prevent discharge of the boosted channels in the unselected memory strings.
4. The method of claim 3 , wherein the select transistors in the selected and unselected memory strings are select gate drain (SGD) transistors.
5. The method of claim 1 , wherein programming the selected memory cells comprises:
biasing a data line of the selected memory strings with a program enable voltage; and
biasing access lines of the selected memory cells with a program voltage.
6. The method of claim 5 , wherein programming the selected memory cells further comprises:
biasing data lines of the unselected memory strings with a program inhibit voltage.
7. A method of operating a NAND architecture memory device, comprising:
biasing select gate drain (SGD) transistors in selected and unselected NAND architecture memory strings to maintain the SGD transistors in an off state;
biasing access lines of memory cells in the selected and unselected memory strings while the SGD transistors are in the off state to boost channels of the memory cells in the selected and unselected memory strings;
biasing the SGD transistors in the selected memory strings to enter an on state to drive the boosted channels in the selected memory strings to ground while maintaining the boosted channels in the unselected memory strings; and
programming selected memory cells in the selected memory strings after driving the boosted channels in the selected memory strings to ground.
8. The method of claim 7 , and further comprising:
biasing data lines of the selected memory strings with a program enable voltage; and
biasing data lines of the unselected memory strings with a program inhibit voltage.
9. The method of claim 8 , and further comprising:
biasing access lines of the selected memory cells with a program voltage.
10. A memory device, comprising:
a memory array having a plurality of memory blocks; and
a controller, wherein the controller is adapted to program memory cells in a selected memory block of the memory array by:
concurrently boosting channels in selected memory strings and unselected memory strings of the selected memory block;
driving the boosted channels in the selected memory strings to a reference potential while maintaining the boosted channels in the unselected memory strings; and
programming selected memory cells in the selected memory strings after driving the boosted channels in the selected memory strings to the reference potential.
11. The memory device of claim 10 , wherein the memory device is a NAND architecture memory device.
12. The memory device of claim 10 , wherein the memory array is a NAND architecture non-volatile memory array.
13. The memory device of claim 10 , wherein the memory device is a three-dimensional (3D) NAND architecture memory device.
14. The memory device of claim 10 , wherein the controller is adapted to apply a first select gate drain (SGD) bias voltage to control gates of SGD devices in the selected and unselected memory strings, wherein the first SGD bias voltage maintains the SGD devices in an off state.
15. The memory device of claim 14 , wherein the controller is adapted to apply a pass voltage to access lines of the memory cells in the selected and unselected memory strings while the SGD devices are in the off state.
16. The memory device of claim 15 , wherein the controller is adapted to apply a second SGD bias voltage to the control gates of the SGD devices in the selected and unselected memory strings, wherein the second SGD bias voltage causes the SGD devices in the selected memory strings to enter an on state to discharge the boosted channels in the selected memory strings.
17. The memory device of claim 16 , wherein the second SGD bias voltage maintains the SGD devices in the unselected memory strings in the off state to maintain the boosted channels in the unselected memory strings.
18. The memory device of claim 10 , wherein the controller is adapted to apply a program enable voltage to data line of the selected memory strings, and apply a program voltage to access lines of the selected memory cells.
19. The memory device of claim 18 , wherein the controller is adapted to apply a program inhibit voltage to data lines of the unselected memory strings.
20. A three-dimensional NAND architecture memory device, comprising:
a three-dimensional memory array having a plurality of memory blocks; and
a controller, wherein the controller is adapted to program memory cells in a selected memory block of the three-dimensional memory array by:
biasing select transistors in selected and unselected NAND architecture memory strings to maintain the select transistors in an off state;
biasing access lines of memory cells in the selected and unselected memory strings while the select transistors are in the off state to boost channels of the memory cells in the selected and unselected memory strings;
biasing the select transistors in the selected memory strings to enter an on state to drive the boosted channels in the selected memory strings to a reference potential while maintaining the boosted channels in the unselected memory strings; and
programming selected memory cells in the selected memory strings after driving the boosted channels in the selected memory strings to the reference potential.
21. The three-dimensional NAND architecture memory device of claim 20 , wherein the select transistors in the selected and unselected NAND architecture memory strings are select gate drain (SGD) transistors.