IP Library Granted Patent US 11,100,996
Granted Patent B2
US 11,100,996 · App. 15/690,889 · Granted Aug 24, 2021

Log data storage for flash memory

Inventors: Paolo Papa (Naples, IT); Luigi Esposito (Piano di Sorrento, IT); Massimo Iaculo (San Marco Evangelista, IT); Eric Kwok Fung Yuen (Dublin, CA); Gerard J. Perdaems (Boise, ID)
Assignee: Micron Technology, Inc.
G11C16/10G06F3/0604G06F3/064G06F3/0619G06F3/0643G06F3/0659G06F3/0679G06F11/079G06F11/0727G06F11/0778G11C16/0483
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Quick Facts
Patent No.
US 11,100,996
App. No.
15/690,889
Granted
Aug 24, 2021
Kind
B2
Abstract

Devices and techniques for managing flash memory are disclosed herein. A memory controller may receive a first program request comprising first host data to be written to the flash memory. The flash memory may comprise a number of storage units with each storage unit comprising a number of storage sub-units. If the first host data is less than a remainder threshold, the memory controller may generate a first program data unit comprising the first host data and first log data describing the flash memory. The memory controller may program the program data unit to the first storage unit of the flash memory, where the first log data is written to a first storage sub-unit of the number of storage sub-unit. The memory controller may also store an indication that the first storage sub-unit is invalid.

Claims (67)

1. A method for managing flash memory, the method comprising:

receiving a first, program request comprising first host data to be written to the flash memory, the flash memory comprising a number of pages, wherein a first page of the number of pages comprises a number of sectors;

determining whether the first host data can be written to the first page without using a portion of the sectors of the first page;

in response to determining that the first host data can be written to the first page without using the portion of the sectors of the first page, generating a first program data unit, wherein the first program data unit comprises the first host data and first log data describing the flash memory;

programming the first program data unit to the first page of the flash memory, wherein the first log data is written to a first sector of the first page; and

storing an indication that the first log data at the first sector is to be discarded in a garbage collection cycle for the first page.

2. The method of claim 1 , further comprising:

initiating a garbage collection cycle for the flash memory; and

discarding the first log data from the first sector.

3. The method of claim 1 , further comprising:

receiving a log data request;

reading at least the first sector to obtain the first log data; and

sending a log data reply comprising the first log data.

4. The method of claim 1 , wherein storing an indication that the first sector is to be discarded in a garbage collection cycle for the first page comprises storing an indication that the first sector is invalid.

5. The method of claim 1 , further comprising:

detecting a critical event related to the flash memory;

generating a second program data unit comprising second log data describing ash memory;

programming the second program data unit at least in part to a second sector, wherein the second sector is of a second page of the number of pages; and

storing an indication that the second sector is to be discarded in a garbage collection cycle for the first page.

6. The method of claim 5 , wherein detecting the critical event comprises detecting a power interruption to the flash memory.

7. The method of claim 5 , wherein the second log data comprises at least a portion of a logical block map describing the flash memory.

8. A flash memory comprising:

a flash memory, comprising a set of parallel-programmable pages;

a memory controller configured to perform operations comprising:

receiving a first program request comprising first host data to be written to the flash memory;

determining whether the first host data can be written to a first set of pages of the flash memory without using a portion of the pages of the first set of pages, wherein each of the first set of pages belongs to a different block of a number of parallel-programmable blocks;

in response to determining that the first host data can be written to the first set of pages without using the portion of the pages of the first set of pages, generating a first program data unit, wherein the first program data unit comprises the first host data and first log data describing the flash memory;

programming the first program data unit to a first set of pages of the flash memory in parallel, wherein each of the first set of pages belongs to a different block of a number of paralle programmable blocks, and wherein the first log data is written to a first page of the first set of pages; and

storing an indication that the first g data at the first page is to be discarded in a garbage collection cycle for the first set of pages.

9. The flash memory of claim 8 , wherein the memory controller is further configured to perform operations comprising:

initiating a garbage collection cycle for the flash memory; and

discarding the first log data from the first page.

10. The flash memory of claim 8 , wherein the memory controller is further configured to perform operations comprising:

receiving a log data request;

reading at least the first page to obtain the first log data; and

sending a log data reply comprising the first log data.

11. The flash memory of claim 8 , wherein storing an indication that the first page is to be discarded in a garbage collection cycle for the first set of pages comprises storing an indication that the first page is invalid.

12. The flash memory of claim 8 , wherein the memory controller is further configured to perform operations comprising:

detecting a critical event related to the flash memory;

generating a second program data unit comprising second log data describing the flash memory after the critical event;

programming the second program data unit at least in part to a second page of a second set of parallel-programmable pages, wherein each of the second set of parallel-programmable pages belongs to a different block of a number of parallel-programmable blocks of the flash memory; and

storing an indication that the second page is to be discarded in a garbage collection cycle for the first set of pages.

13. The flash memory of claim 12 , wherein detecting the critical event comprises detecting a power interruption to the flash memory.

14. The flash memory of claim 12 , wherein the second log data comprises at least a portion of a logical block map describing the flash memory.

15. A flash memory comprising:

a flash memory comprising a number of pages, wherein a first page of the number of pages comprises a number of sectors; and

a memory controller configured to perform operations comprising:

receiving a first program request comprising first host data to be written to the flash memory; and

if the first host data can be written to the first page without using a portion of the sectors of the first page:

generating a first program data unit, wherein the first program data unit comprises the first host data and first log data describing the flash memory;

programming the first program data unit to the first page, wherein the first log data is written to a first sector of the first page; and

storing an indication that the first sector of the first page is to be discarded in a garbage collection cycle for the first page.

16. The flash memory of claim 15 , wherein the memory controller is further configured to perform operations comprising:

initiating a garbage collection cycle for the flash memory; and

discarding the first log data from the first sector.

17. The flash memory of claim 15 , wherein the memory controller is further configured to perform operations comprising:

receiving a log data request;

reading at least the first sector to obtain the first log data; and

sending a log data reply comprising the first log data.

18. The flash memory of claim 15 , wherein storing an indication that the first page is to be discarded in a garbage collection cycle for the first page comprises storing an indication that the first page is invalid.

19. The flash memory of claim 15 , wherein the memory controller is further configured to perform operations comprising:

detecting a critical event related to the flash memory;

generating a second program data unit comprising second log data describing the flash memory;

programming the second program data unit at least in part to a second sector of a second page of the number of pages; and

storing an indication that the second sector is to be discarded in a garbage collection cycle for the first page.

20. The flash memory of claim 19 , wherein detecting the critical event comprises detecting a power interruption to the flash memory.

21. The flash memory of claim 19 , wherein the second log data comprises at least a portion of a logical block map describing the flash memory.

Assignments (7)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050709/0838 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 24, 2018
From: PAPA, PAOLO; ESPOSITO, LUIGI; IACULO, MASSIMO; YUEN, ERIC KWOK FUNG; PERDAEMS, GERARD J
To: MICRON TECHNOLOGY, INC.
Reel/Frame 046692/0547 →
RELEASE OF SECURITY INTEREST Recorded Jul 20, 2018
From: U.S. BANK NATIONAL ASSOCIATION, AS AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 046597/0333 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
SUPPLEMENT NO. 6 TO PATENT SECURITY AGREEMENT Recorded Nov 1, 2017
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 044653/0333 →
SUPPLEMENT NO. 6 TO PATENT SECURITY AGREEMENT Recorded Nov 1, 2017
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 044348/0253 →
Cited By (1)
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