Flash memory block retirement policy
View Patent ↗Devices and techniques for a flash memory block retirement policy are disclosed herein. In an example embodiment, a first memory block is removed from service in response to encountering a read error in the first memory block that exceeds a first error threshold. Recoverable data is copied from the first memory block to a second memory block. During each of multiple iterations, the first memory block is erased and programmed, and each page of the first memory block is read. In response to none of the pages exhibiting a read error that exceeds a second error threshold during the multiple iterations, the first memory block is returned to service.
1. A method for implementing a memory block retirement policy for a flash memory array, the method comprising:
in response to encountering a read error in a first memory block of the flash memory array that exceeds a first error threshold:
provisionally removing the first memory block from service, the first memory block comprising multiple memory pages;
copying recoverable data of the first memory block to a second memory block of the flash memory array;
after the removing of the first memory block from service, and the copying of the recoverable data of the first memory block to the second memory block, during each of multiple iterations:
erasing the first memory block;
programming the first memory block after the erasing of the first memory block;
reading the multiple memory pages of the first memory block after the programming of the first memory block; and
determining whether at least one of the multiple memory pages exhibits a read error exceeding a second error threshold during the reading of the multiple memory pages; and
returning the first memory block to service in response to none of the multiple memory pages exhibiting a read error exceeding the second error threshold during the reading of the multiple memory pages during the multiple iterations,
wherein the programming the first memory block after the erasing of the first memory block during each of the multiple iterations includes varying the data programmed to each of the multiple pages during each of the multiple iterations.
2. The method of claim 1 , further comprising:
permanently retiring the first memory block from service in response to at least one of the multiple memory pages exhibiting a read error exceeding the second error threshold during the multiple iterations.
3. The method of claim 1 , wherein the second memory block comprises a memory block from a pool of free memory blocks, and the method further comprises:
placing the second memory block in service after the copying of the recoverable data of the first memory block to the second memory block.
4. The method of claim 1 , wherein the returning of the first memory block to service comprises returning the first memory block to a pool of free memory blocks.
5. The method of claim 1 , wherein the first error threshold comprises a correctable error threshold, and the recoverable data of the first memory block comprises all data of the first memory block.
6. The method of claim 1 , wherein the first error threshold comprises an uncorrectable error threshold, and the recoverable data of the first memory block comprises less than all data of the first memory block.
7. The method of claim 1 , wherein the encountering of the read error in the first memory block occurs during a read operation employing a default read voltage for the control gate of each memory cell of the first memory block.
8. The method of claim 1 , wherein the encountering of the read error in the first memory block occurs during a read operation employing a read voltage that is offset from a default read voltage for the control gate of each memory cell of the first memory block.
9. The method of claim 1 , wherein the reading of the multiple memory pages of the first memory block comprises varying a read voltage for at least one of the multiple memory pages during an iteration of the multiple iterations.
10. The method of claim 9 , wherein the varying of the read voltage is employed to increase a read window budget during the iteration of the multiple iterations.
11. The method of claim 1 , further comprising:
receiving, from a host device, a read command to read the first memory block;
performing a read operation on the first memory block in response to receiving the read command, wherein the encountering of the read error occurs during the read operation.
12. The method of claim 1 , wherein the encountering of the read error occurs during an error scrubbing process performed on the first memory block.
13. The method of claim 1 , wherein the multiple iterations occur during one or more periods of time during which commands from a host for access to the flash memory array are not processed.
14. A data storage system comprising:
a flash memory array comprising multiple memory blocks, each of the multiple memory blocks comprising multiple memory pages;
one or more hardware processors; and
a memory storing instructions that, when executed by at least one of the one or more hardware processors, cause the data storage system to perform operations comprising:
in response to encountering a read error in a first memory block of the flash memory array that exceeds a first error threshold:
removing the first memory block from service, the first memory block comprising multiple memory pages;
copying recoverable data of the first memory block to a second memory block of the flash memory array;
after the removing of the first memory block from service, and the copying of the recoverable data of the first memory block to the second memory block, during each of multiple iterations:
erasing the first memory block;
programming the first memory block after the erasing of the first memory block;
reading the multiple memory pages of the first memory block after the programming of the first memory block; and
determining whether at least one of the multiple memory pages exhibits a read error exceeding a second error threshold during the reading of the multiple memory pages; and
returning the first memory block to service in response to none of the multiple memory pages exhibiting a read error exceeding the second error threshold during the reading of the multiple memory pages during the multiple iterations,
wherein the programming the first memory block after the erasing of the first memory block during each of the multiple iterations includes varying the data programmed to each of the multiple pages during each of the multiple iterations.
15. The data storage system of claim 14 , wherein:
the first error threshold comprises an uncorrectable error threshold; and
the encountering of the read error in the first memory block persists after an error handling process is performed on the first memory block.
16. The data storage system of claim 14 , wherein the reading of the multiple memory pages of the first memory block comprises varying a read voltage for at least one of the multiple memory pages during an iteration of the multiple iterations.
17. The data storage system of claim 16 , wherein the reading of the multiple memory pages of the first memory block comprises reading each of the multiple memory pages multiple times while varying the read voltage during the iteration of the multiple iterations.
18. The data storage system of claim 14 , wherein the flash memory array comprises a multi-level cell NAND memory array.
19. The data storage system of claim 14 , wherein:
the flash memory array comprises a three-dimensional NAND memory array; and
each of the multiple memory pages of the three-dimensional NAND memory array comprises a vertically-oriented two-dimensional array of memory cells.
20. A non-transitory computer-readable data storage storing instructions that, when executed by one or more hardware processors of a data storage system, cause the data storage system to perform operations comprising:
in response to encountering a read error in a first memory block of a flash memory array that exceeds a first error threshold:
removing the first memory block from service, the first memory block comprising multiple memory pages;
copying recoverable data of the first memory block to a second memory block of the flash memory array:
after the removing of the first memory block from service, and the copying of the recoverable data of the first memory block to the second memory block, during each of multiple iterations:
erasing the first memory block;
programming the first memory block after the erasing of the first memory block;
reading the multiple memory pages of the first memory block after the programming of the first memory block; and
determining whether at least one of the multiple memory pages exhibits a read error exceeding a second error threshold during the reading of the multiple memory pages; and
returning the first memory block to service in response to none of the multiple memory pages exhibiting a read error exceeding the second error threshold during the reading of the multiple memory pages during the multiple iterations,
wherein the programming the first memory block after the erasing of the first memory block during each of the multiple iterations includes varying the data programmed to each of the multiple pages during each of the multiple iterations.