RANDOM ACCESS MEMORY POWER SAVINGS
Devices and techniques for random access memory power savings are disclosed herein. Data contained in RAM is compressed in response to obtaining a trigger. Here, the RAM organized into several discrete hardware components with a corresponding power control. The data contained in the RAM is replaced with the compressed data to free a discrete hardware component of the RAM. The discrete hardware component is then powered down via the corresponding power control.
1 . A device for random access memory power (RAM) savings, the device comprising processing circuitry to:
obtain a trigger;
compress, in response to the trigger, data contained in a RAM to create compressed data, the RAM organized into several discrete hardware components with a corresponding power control;
replace the data contained in the RAM with the compressed data in the RAM freeing a discrete hardware component of the RAM; and
power down the discrete hardware component via the corresponding power control.
2 . The device of claim 1 , wherein the discrete hardware component is a bank.
3 . The device of claim 1 , wherein the discrete hardware component is a chip.
4 . The device of claim 1 , wherein the discrete hardware component is a bus.
5 . The device of claim 1 , wherein the trigger is initiation of a RAM maintenance operation.
6 . The device of claim 5 , wherein the RAM maintenance operation is a de-fragmentation operation.
7 . The device of claim 1 , wherein the trigger is host inactivity, wherein the host is a device communicatively coupled to the RAM when in operation.
8 . The device of claim 7 , wherein the host inactivity is triggered when a display of the host is off.
9 . The device of claim 1 , wherein the trigger is a low-power state of a host, wherein the host is a device communicatively coupled to the RAM when in operation, and wherein the host is operable away from mains power.
10 . The device of claim 1 , wherein the device is a mobile management unit (MMU) of a host, wherein the host is a device communicatively coupled to the RAM when in operation.
11 . A method for random access memory power (RAM) savings, the method comprising:
obtaining a trigger;
compressing, in response to the trigger, data contained in a RAM to create compressed data, the RAM organized into several discrete hardware components with a corresponding power control;
replacing the data contained in the RAM with the compressed data in the RAM freeing a discrete hardware component of the RAM; and
powering down the discrete hardware component via the corresponding power control.
12 . The method of claim 11 , wherein the discrete hardware component is a bank.
13 . The method of claim 11 , wherein the discrete hardware component is a chip.
14 . The method of claim 11 , wherein the discrete hardware component is a bus.
15 . The method of claim 11 , wherein the trigger is initiation of a RAM maintenance operation.
16 . The method of claim 15 , wherein the RAM maintenance operation is a de-fragmentation operation.
17 . The method of claim 11 , wherein the trigger is host inactivity, wherein the host is a device communicatively coupled to the RAM when in operation.
18 . The method of claim 17 , wherein the host inactivity is triggered when a display of the host is off.
19 . The method of claim 11 , wherein the trigger is a low-power state of a host, wherein the host is a device communicatively coupled to the RAM when in operation, and wherein the host is operable away from mains power.
20 . The method of claim 11 , wherein the operations of obtaining the trigger, compressing the data, replacing the data and powering down the discrete hardware component are performed by a mobile management unit (MMU) of a host, wherein the host is a device communicatively coupled to the RAM when in operation.
21 . At least one machine readable medium including instructions that, when executed by processing circuitry, cause the processing circuitry to perform operations comprising:
obtaining a trigger;
compressing, in response to the trigger, data contained in a RAM to create compressed data, the RAM organized into several discrete hardware components with a corresponding power control;
replacing the data contained in the RAM with the compressed data in the RAM freeing a discrete hardware component of the RAM; and
powering down the discrete hardware component via the corresponding power control.
22 . The machine readable medium of claim 21 , wherein the discrete hardware component is a bank.
23 . The machine readable medium of claim 21 , wherein the discrete hardware component is a chip.
24 . The machine readable medium of claim 21 , wherein the discrete hardware component is a bus.
25 . The machine readable medium of claim 21 , wherein the trigger is initiation of a RAM maintenance operation.
26 . The machine readable medium of claim 25 , wherein the RAM maintenance operation is a de-fragmentation operation.
27 . The machine readable medium of claim 21 , wherein the trigger is host inactivity, wherein the host is a device communicatively coupled to the RAM when in operation.
28 . The machine readable medium of claim 27 , wherein the host inactivity is triggered when a display of the host is off.
29 . The machine readable medium of claim 21 , wherein the trigger is a low-power state of a host, wherein the host is a device communicatively coupled to the RAM when in operation, and wherein the host is operable away from mains power.
30 . The machine readable medium of claim 21 , wherein the operations of obtaining the trigger, compressing the data, replacing the data and powering down the discrete hardware component are performed by a mobile management unit (MMU) of a host, wherein the host is a device communicatively coupled to the RAM when in operation.