Apparatuses and methods for shielded memory architecture

1. An apparatus, comprising:

a first memory cell comprising a storage component having a first end coupled to a plate line and a second end coupled to a digit line; and

a second memory cell comprising a storage component having a first end coupled to a digit line and a second end coupled to a plate line;

wherein the digit line of the second memory cell is adjacent to the plate line of the first memory cell; and

wherein the digit line coupled to the second end of the first memory cell is on an opposite side of the first and second memory cells as the digit line coupled to the first end of the second memory cell.

2. The apparatus of claim 1 , wherein the digit line of the first memory cell is adjacent to the plate line of the second memory cell.

3. The apparatus of claim 1 , further comprising:

a third memory cell comprising a storage component having a first end coupled to a plate line and a second end coupled to a digit line;

wherein the digit line of the second memory cell is adjacent to the plate line of the third memory cell.

4. The apparatus of claim 3 , further comprising:

a first layer of memory cells; and

a second layer of memory cells that includes the first, second, and third memory cells.

5. The apparatus of claim 4 , further comprising:

a fourth memory cell included in the first layer of memory cells, the fourth memory cell comprising a storage component having a first end coupled to a plate line and a second end coupled to a digit line;

wherein the digit line of the fourth memory cell and the digit line of the second memory cell are combined into a shared digit line.

6. The apparatus of claim 4 , further comprising:

a fourth memory cell included in the first layer of memory cells, the fourth memory cell comprising a storage component having a first end coupled to a digit line and a second end coupled to a plate line;

wherein the digit line of the second memory cell is adjacent to the plate line of the fourth memory cell.

7. The apparatus of claim 1 , wherein the first end of the first storage component of the first memory cell is coupled to the plate line through a first selection component.

8. The apparatus of claim 7 , wherein the second end of the first storage component of the first memory cell is coupled to the digit line through a second selection component.

9. The apparatus of claim 1 , wherein the first and second storage components are dielectric capacitors.

10. The apparatus of claim 1 , wherein the first and second storage components are ferroelectric capacitors.

11. An apparatus, comprising:

a first layer of memory cells;

a second layer of memory cells underlying the first layer of memory cells;

a first memory cell included in the first layer of memory cells, the first memory cell comprising a storage component having a first end coupled to a plate line and a second end coupled to a digit line; and

a second memory cell included in the second layer of memory cells, the second memory cell comprising a storage component having a first end coupled to a digit line and a second end coupled to a plate line;

wherein the digit line of the first memory cell and the digit line of the second memory cell are combined between the first and second memory cells into a shared digit line.

12. The apparatus of claim 11 , comprising:

a third memory cell included in the first layer of memory cells, the third memory cell comprising a storage component having a first end coupled to a digit line and a second end coupled to a plate line; and

a fourth memory cell included in the second layer of memory cells, the fourth memory cell comprising a storage component having a first end coupled to a plate line and a second end coupled to a digit line; wherein

the plate line of the third memory cell and the plate line of the fourth memory cell are combined into a shared plate line; and

the shared digit line of the first and second memory cell is adjacent to the shared plate line of the third and fourth plate line.

13. The apparatus of claim 12 , comprising:

a fifth memory cell included in the first layer of memory cells, the fifth memory cell comprising a storage component having a first end coupled to a digit line and a second end coupled to a plate line; and

a sixth memory cell included in the second layer of memory cells, the sixth memory cell comprising a storage component having a first end coupled to a plate line and a second end coupled to a digit line; wherein

the plate line of the fifth memory cell and the plate line of the sixth memory cell are combined into a shared plate line; and

the shared digit line of the first and second memory cell is adjacent to the shared plate line of the fifth and sixth plate line.

14. The apparatus of claim 11 , wherein

a second end of the storage component of the first memory cell is coupled to the digit line through a first selection component; and

a second end of the storage component of the second memory cell is coupled to the plate line through a second selection component.

15. The apparatus of claim 14 , wherein

a first end of the storage component of the first memory cell is coupled to the plate line through a third selection component; and

a first end of the storage component of the second memory cell is coupled to the digit line through a fourth selection component.

16. An apparatus, comprising:

a first memory layer;

a second memory layer underlying the first memory layer;

a memory cell including a first storage component in the first memory layer and a second storage component in the second memory layer; wherein

the first storage component includes a first end coupled to a plate line and a second end coupled to a digit line;

the second storage component includes a first end coupled to a plate line and a second end coupled to a digit line; and

the digit line of the first storage component is adjacent to the plate line of the second storage component;

wherein the first and second storage components are aligned along a same axis.

17. The apparatus of claim 16 , wherein the memory cell is a first memory cell, the apparatus further comprising:

a second memory cell including a first storage component in the first memory layer and a second storage component in the second memory layer; wherein

the first storage component of the second memory cell includes a first end coupled to a digit line and a second end coupled to a plate line;

the second storage component of the second memory cell includes a first end coupled to a digit line and a second end coupled to a plate line; and

the digit line of the first storage component of the first memory cell is adjacent to the plate line of the first storage component of the second memory cell.

18. The apparatus of claim 17 , further comprising:

a third memory cell including a first storage component in the first memory layer and a second storage component in the second memory layer; wherein

the first storage component of the third memory cell includes a first end coupled to a digit line and a second end coupled to a plate line;

the second storage component of the third memory cell includes a first end coupled to a digit line and a second end coupled to a plate line; and

the digit line of the first storage component of the first memory cell is adjacent to the plate line of the first storage component of the third memory cell.

19. The apparatus of claim 16 , wherein

a second end of the first storage component is coupled to the digit line through a first selection component; and

a second end of the second component is coupled to the digit line through a second selection component.

20. The apparatus of claim 19 , wherein

a first end of the second storage component is coupled to the plate line through a third selection component; and

a first end of the second storage component is coupled to the plate line through a fourth selection component.