METHOD FOR BASE CONTACT LAYOUT, SUCH AS FOR MEMORY

1 . A memory device, comprising:

an array of memory cells comprising a plurality of electrodes individually comprising one or more base contact areas at a common depth, wherein a subset of the one or more base contact areas are electrically connected to a respective electrically conductive interconnect that provides an electrically conductive path to one or more selector transistors associated with one or more memory cells of the array.

2 . The memory device of claim 1 , wherein subsets of contact areas for electrodes of the plurality of electrodes are coupled with electrically conductive interconnects in a substantially alternating pattern.

3 . The memory device of claim 2 , wherein the substantially alternating pattern comprises a contact area of an electrode being coupled with the respective electrically conductive interconnect if a corresponding contact area of an immediately adjacent electrode is not coupled with an electrically conductive interconnect.

4 . The memory device of claim 3 , wherein the one or more selector transistors comprise one or more bipolar junction transistors, and wherein the respective electrically conductive interconnect comprises an electrically conductive interconnect coupled between the contact area and a component of the one or more bipolar junction transistors.

5 . The memory device of claim 1 , wherein the array of memory cells comprises an array of phase change memory cells.

6 . The memory device of claim 1 , wherein the array of memory cells comprises a chalcogenide material.

7 . The memory device of claim 1 , wherein the plurality of electrodes comprise a plurality of word-line electrodes.

8 . The memory device of claim 1 , wherein the plurality of electrodes comprise a plurality of bit-line electrodes.

9 . A memory device, comprising a plurality of word-line interconnect portions extending in a first direction, each word-line interconnect portion tapering from a first width to a second width less than the first width;

a plurality of base interconnect areas associated with the plurality of word-line interconnect portions, each base interconnect area having a first dimension extending in the first direction that is larger than the second width that extends in a second direction different from the first direction, at least one base interconnect area of the plurality of base interconnect areas contacting a first pair of base contact pillars; and

a second pair of base contact pillars different from the first pair of base contact pillars positioned between base interconnect areas that are located along the second direction, the second pair of base contact pillars being spaced apart from the plurality of word-line interconnect portions.

10 . The memory device of claim 9 , further comprising:

one or more selector transistors associated with one or more memory cells of a memory array, wherein the one or more selector transistors each comprise a base component associated with a respective base interconnect area of one of the plurality of base interconnect areas.

11 . The memory device of claim 10 , wherein the base component comprises an epitaxial semiconductor material deposited over a collector material.

12 . The memory device of claim 10 , wherein the base component comprises a silicon material deposited over a collector material.

13 . The memory device of claim 10 , further comprising:

one or more trenches formed in the epitaxial semiconductor material.

14 . The memory device of claim 13 , wherein the one or more trenches are formed using a shallow-trench isolation configuration.

15 . The memory device of claim 9 , further comprising:

a plurality of isolation trenches formed on opposing sides of the base interconnect areas, the plurality of isolation trenches being elongated in the second direction.

16 . The memory device of claim 15 , further comprising:

one or more memory cells formed on the opposing sides of the base interconnect areas, the one or more memory cells immediately adjacent to the plurality of isolation trenches.

17 . The memory device of claim 9 , wherein:

the first direction comprises a word-line direction; and

the second direction comprises a bit-line direction.

18 . The memory device of claim 9 , wherein the second pair of base contact pillars is associated with a first word-line interconnect portion, and wherein one of the base interconnect areas located along the second direction is associated with a second word-line interconnect portion different from the first word-line interconnect portion.

19 . The memory device of claim 9 , wherein the first pair of base contact pillars is coupled with the plurality of word-line interconnect portions through the at least one base interconnect area.

20 . A memory device, comprising

a plurality of word-line interconnect portions extending in a first direction, each word-line interconnect portion tapering from a first width to a second width less than the first width; and

a plurality of base interconnect areas for the plurality of word-line interconnect portions, wherein each word-line interconnect portion has a plurality of associated base interconnect areas, wherein at least one base interconnect area contacts a first pair of base contact pillars, wherein a second pair of base contact pillars different from the first pair of base contact pillars is positioned between base interconnect areas located along a second direction different from the first direction, the second pair of base contact pillars being separated from the plurality of word-line interconnect portions, each base interconnect area having a first dimension extending in the first direction that is at least three times larger than the second width of the word-line interconnect portions, the second width extending in the second direction; and

wherein each base interconnect area is longer along the first direction than along the second direction.