IP Library Granted Patent US 10,522,229
Granted Patent B2
US 10,522,229 · App. 15/691,584 · Granted Dec 31, 2019

Secure erase for data corruption

Inventors: Ting Luo (Santa Clara, CA); Kulachet Tanpairoj (Santa Clara, CA); Harish Singidi (Fremont, CA); Jianmin Huang (San Carlos, CA); Preston Thomson (Boise, ID); Sebastien Andre Jean (Meridian, ID)
Assignee: Micron Technology, Inc.
G11C16/16G11C11/5635G11C16/0483G11C16/08G11C16/3445G11C11/5671G11C16/3409H01L27/11556H01L27/11582
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Quick Facts
Patent No.
US 10,522,229
App. No.
15/691,584
Granted
Dec 31, 2019
Kind
B2
Abstract

Disclosed in some examples are systems, methods, memory devices, and machine readable mediums for a fast secure data destruction for NAND memory devices that renders data in a memory cell unreadable. Instead of going through all the erase phases, the memory device may remove sensitive data by performing only the pre-programming phase of the erase process. Thus, the NAND doesn't perform the second and third phases of the erase process. This is much faster and results in data that cannot be reconstructed. In some examples, because the erase pulse is not actually applied and because this is simply a programming operation, data may be rendered unreadable at a per-page level rather than a per-block level as in traditional erases.

Claims (60)

1. A method comprising:

determining, at a memory device, that a value stored in a page of a NAND array of the memory device is to be destroyed; and

in response to the determining, destroying the value in the page without destroying any other data in a block containing the page by applying only a pre-programming pulse to memory cells of the page, the pre-programming pulse bringing a voltage level of the memory cells of the page to a predetermined voltage level.

2. The method of claim 1 , comprising:

subsequent to applying the pre-programming pulse:

determining that the page is to be erased; and

responsive to determining that the memory cell is to be erased:

refraining from applying the pre-programming pulse to the memory cells in the page;

applying an erase pulse to the memory cells in the page; and

verifying that the page is erased.

3. The method of claim 1 , wherein determining that the value is to be destroyed comprises receiving a command from a host over a communications interface.

4. The method of claim 1 , wherein determining that the value stored in the page of the NAND array of the memory device is to be destroyed comprises:

receiving a delete request from a host over a communications interface for a logical block address mapped to the page;

determining that the logical block address is classified as sensitive; and

in response to receiving the delete request and determining that the logical block address is classified as sensitive, determining that the value stored in the page is to be destroyed.

5. The method of claim 4 , comprising:

responsive to receiving the delete request, marking the memory cell as unallocated.

6. A memory device comprising:

a NAND memory array;

a memory controller configured to perform operations comprising:

determining that a value stored in a page of the NAND memory array of the memory device is to be destroyed; and

in response to the determining, destroying the value in the page without destroying any other data in a block containing the page by applying only a pre-programming pulse to memory cells of the page, the pre-programming pulse bringing a voltage level of the memory cells of the page to a predetermined voltage level.

7. The memory device of claim 6 , wherein the memory controller is further configured to perform operations comprising:

subsequent to applying the pre-programming pulse:

determining that the memory cell is to be erased; and

responsive to determining that the memory cell is to be erased:

refraining from applying the pre-programming pulse to the memory cells in the page;

applying an erase pulse to the memory cells in the page; and

verifying that the page is erased.

8. The memory device of claim 6 , wherein the operations of determining that the value is to be destroyed comprises operations of receiving a command from a host over a communications interface.

9. The memory device of claim 6 , wherein the operations of determining that the value stored in the page of the NAND array of the memory device is to be destroyed comprises:

receiving a delete request from a host over a communications interface for a logical block address mapped to the page;

determining that the logical block address is classified as sensitive; and

in response to receiving the delete request and determining that the logical block address is classified as sensitive, determining that the value stored in the page of the memory device is to be destroyed.

10. The memory device of claim 9 , comprising:

responsive to receiving the delete request, marking the memory cell as unallocated.

11. A non-transitory machine-readable medium, comprising instructions, that when executed by the machine, cause the machine to perform operations comprising:

determining that a value stored in a page of a NAND array a memory device is to be destroyed; and

in response to the determining, destroying the value in the page without destroying any other data in a block containing the page by applying only a pre-programming pulse to memory cells of the page, the pre-programming pulse bringing a voltage level of the memory cells of the page to a predetermined voltage level.

12. The non-transitory machine-readable medium of claim 11 ,

wherein the operations further comprise:

subsequent to applying the pre-programming pulse:

determining that the memory cell is to be erased; and

responsive to determining that the memory cell is to be erased:

refraining from applying the pre-programming pulse to the memory cells in the page;

applying an erase pulse to the memory cells in the page; and

verifying that the page is erased.

13. The non-transitory machine-readable medium of claim 11 , wherein the operations of determining that the value is to be destroyed comprises operations of receiving a command from a host over a communications interface.

14. The method of claim 1 , further comprising:

receiving a command identifying a first logical block address of the value;

determining that the page is mapped to the first logical block address and a second logical block address; and

moving a value corresponding to the second logical block address to a new page prior to destroying the value in the memory cell.

15. The memory device of claim 6 , wherein the operations further comprise:

receiving a command identifying the value;

determining that the page includes the value and a second value not identified for destruction; and

moving the second value to a new page prior to destroying the value in the memory cell.

16. The non-transitory machine-readable medium of claim 11 , wherein the operations further comprise:

receiving a command identifying the value;

determining that the page includes the value and a second value not identified for destruction; and

moving the second value to a new page prior to destroying the value in the memory cell.

Assignments (7)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 22, 2019
From: LUO, TING; TANPAIROJ, KULACHET; SINGIDI, HARISH REDDY; HUANG, JIANMIN; THOMSON, PRESTON; JEAN, SEBASTIEN ANDRE
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050792/0789 →
RELEASE OF SECURITY INTEREST Recorded Oct 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050709/0838 →
RELEASE OF SECURITY INTEREST Recorded Jul 20, 2018
From: U.S. BANK NATIONAL ASSOCIATION, AS AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 046597/0333 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
SUPPLEMENT NO. 6 TO PATENT SECURITY AGREEMENT Recorded Nov 1, 2017
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 044348/0253 →
SUPPLEMENT NO. 6 TO PATENT SECURITY AGREEMENT Recorded Nov 1, 2017
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 044653/0333 →
Continuity (1)
Related Publication 20190066799A1 · Feb 28, 2019
Cited By (1)
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