Predicting and controlling power consumption for a storage device
A storage device includes a nonvolatile semiconductor memory and a controller. The controller is configured to predict power consumption that is required to carry out operations in accordance with access pattern and throughput received from a host, notify the predicted power consumption to the host, determine operating resources of at least one of the nonvolatile semiconductor memory and the controller to carry out the operations, on the basis of the permissible power consumption received from the host, and carry out the operations using the determined operating resources.
1. A storage device comprising:
a nonvolatile semiconductor memory;
a temperature sensor; and
a controller configured to
in response to a request to predict power consumption, the request received from a host and designating access pattern and throughput,
predict power consumption that is required to carry out operations based on temperature of the storage device detected by the temperature sensor, the access pattern designated in the request, the throughput designated in the request, and an overprovisioning ratio, an amount of increased power consumption with respect to an amount of increased performance level being larger in a case where the overprovisioning ratio is a first value than in a case where the overprovisioning ratio is a second value, the second value being greater than the first value,
notify the predicted power consumption to the host,
receive permissible power consumption from the host, the permissible power consumption being determined on the basis of the predicted power consumption notified to the host,
determine operating resources of at least one of the nonvolatile semiconductor memory and the controller to carry out the operations, on the basis of the permissible power consumption received from the host, and
carry out the operations using the determined operating resources.
2. The storage device according to claim 1 , wherein
the nonvolatile semiconductor memory includes a plurality of channels accessible in parallel, each of which is individually connected to the controller through a bus and includes one or more nonvolatile semiconductor memory chips, and
determining the operating resources includes determining a number of channels to be used in parallel for the operations.
3. The storage device according to claim 1 , wherein
the nonvolatile semiconductor memory includes a plurality of banks accessible in an interleaved manner, each of the banks including one or more nonvolatile semiconductor chips, and
determining the operating resources includes determining a number of banks to be accessed in parallel in the interleaved manner for the operations.
4. The storage device according to claim 1 , wherein
the nonvolatile semiconductor memory includes a plurality of memory chips operating in parallel with each other, and
determining the operating resources includes determining a number of memory chips to operate in parallel for the operations.
5. The storage device according to claim 1 , wherein
the controller includes a plurality of processors that are capable of operating in parallel, and
determining the operating resources includes determining a number of processors to be used in parallel for the operations.
6. The storage device according to claim 1 , wherein
the access pattern indicates at least one of a ratio of a number of read operations to a number of write operations and continuity of addresses in the storage device to be accessed.
7. The storage device according to claim 1 , wherein
the controller is further configured to encode data to be written into the nonvolatile semiconductor memory at a selected code rate, which corresponds to a ratio of a size of data before encoding to a size of the data after encoding, and predict the power consumption based also on the selected code rate.
8. The storage device according to claim 1 , wherein
the nonvolatile semiconductor memory includes one or more nonvolatile semiconductor memory chips, and
the controller is configured to predict the power consumption based also on a processing time required to program each of the nonvolatile semiconductor chips in response to a write command.
9. The storage device according to claim 1 , wherein
the controller is configured to predict the power consumption further based also on a write amplification factor.
10. The storage device according to claim 1 , wherein
the controller is configured to predict the power consumption such that, under a condition that performance levels are same, the power consumption at a first junction temperature is higher than the power consumption at a second junction temperature, the first junction temperature being higher than the second junction temperature.
11. A storage device comprising:
a nonvolatile semiconductor memory;
a temperature sensor; and
a controller configured to
in response to a request to predict power consumption, the request received from a host and designating access pattern and throughput,
predict power consumption that is required to carry out operations based on temperature of the storage device detected by the temperature sensor, the access pattern received from the host, the throughput received from the host, and an overprovisioning ratio, an amount of increased power consumption with respect to an amount of increased performance level being larger in a case where the overprovisioning ratio is a first value than in a case where the overprovisioning ratio is a second value, the second value being greater than the first value,
determine a resource for at least one of the nonvolatile semiconductor memory and the controller for carrying out the operations, based on lesser of the predicted power consumption and permissible power consumption that is received from the host, and
carry out the operations using the determined resource.
12. The storage device according to claim 11 , wherein
the nonvolatile semiconductor memory includes a plurality of channels accessible in parallel, each of which is individually connected to the controller through a bus and includes one or more nonvolatile semiconductor memory chips, and
determining the resource includes determining a number of channels to be used in parallel for the operations.
13. The storage device according to claim 11 , wherein
the nonvolatile semiconductor memory includes a plurality of banks accessible in an interleaved manner, each of the banks including one or more nonvolatile semiconductor chips, and
determining the resource includes determining a number of banks to be accessed in parallel in the interleaved manner for the operations.
14. The storage device according to claim 11 , wherein
the nonvolatile semiconductor memory includes a plurality of memory chips operating in parallel with each other, and
determining the operating resources includes determining a number of memory chips to operate in parallel for the operations.
15. The storage device according to claim 11 , wherein
the controller includes a plurality of processors that are capable of operating in parallel, and
determining the resource includes determining a number of processors to be used in parallel for the operations.
16. The storage device according to claim 11 , wherein
the access pattern indicates at least one of a ratio of a number of read operations to a number of write operations and continuity of addresses in the storage device to be accessed.
17. The storage device according to claim 11 , wherein
the controller is further configured to encode data to be written in the nonvolatile semiconductor memory at a selected code rate, which corresponds to a ratio of a size of data before encoding and a size of the data after encoding, and predict the power consumption based also on the selected code rate.
18. The storage device according to claim 11 , wherein
the nonvolatile semiconductor memory includes one or more nonvolatile semiconductor memory chips, and
the controller is configured to predict the power consumption based also on a processing time required to program each of the nonvolatile semiconductor memory chips in response to a write command.
19. The storage device according to claim 11 , wherein
the controller is configured to predict the power consumption such that, under a condition that performance levels are same, the power consumption at a first junction temperature is higher than the power consumption at a second junction temperature, the first junction temperature being higher than the second junction temperature.