Responding to power loss

1. A method of operating a memory, comprising:

obtaining information indicative of a data value stored in a particular memory cell of the memory;

programming additional data to the particular memory cell;

determining if a power loss to the memory is indicated while programming the additional data to the particular memory cell; and

if a power loss to the memory is indicated, selectively programming one memory cell of a pair of gate-connected non-volatile memory cells responsive to the information indicative of the data value stored in the particular memory cell;

wherein a resulting combination of threshold voltages of the one memory cell of the pair of gate-connected non-volatile memory cells and of the other memory cell of the pair of gate-connected non-volatile memory cells is representative of the information indicative of the data value stored in the particular memory cell.

2. The method of claim 1 , wherein selectively programming the one memory cell of the pair of gate-connected non-volatile memory cells responsive to the information indicative of the data value stored in the particular memory cell comprises:

applying a first voltage level to a first source/drain of the one memory cell of the pair of gate-connected non-volatile memory cells and to a first source/drain of the other memory cell of the pair of gate-connected non-volatile memory cells;

applying a second voltage level higher than the first voltage level to a gate of the one memory cell of the pair of gate-connected non-volatile memory cells and to a gate of the other memory cell of the pair of gate-connected non-volatile memory cells;

applying a third voltage level, higher than the first voltage level and lower than the second voltage level, to a second source/drain of the one memory cell of the pair of gate-connected non-volatile memory cells; and

applying the first voltage level to a second source/drain of the other memory cell of the pair of gate-connected non-volatile memory cells.

3. The method of claim 2 , wherein a combination of the first voltage level, the second voltage level and the third voltage level is selected to cause charge to accumulate in a data-storage structure of the one memory cell during programming of the one memory cell.

4. The method of claim 3 , wherein the combination of the first voltage level, the second voltage level and the third voltage level is further selected to inhibit charge accumulation in a data-storage structure of the other memory cell during programming of the one memory cell.

5. The method of claim 1 , wherein selectively programming the one memory cell of the pair of gate-connected non-volatile memory cells responsive to the information indicative of the data value stored in the particular memory cell comprises programming the one memory cell of the pair of gate-connected non-volatile memory cells if the information indicative of the data value stored in the particular memory cell has a first logic level, and inhibiting programming of the one memory cell of the pair of gate-connected non-volatile memory cells if the information indicative of the data value stored in the particular memory cell has a second logic level different than the first logic level.

6. The method of claim 5 , further comprising programming the other memory cell of the pair of gate-connected non-volatile memory cells if the information indicative of the data value stored in the particular memory cell has the second logic level.

7. The method of claim 1 , wherein selectively programming the one memory cell of the pair of gate-connected non-volatile memory cells responsive to the information indicative of the data value stored in the particular memory cell comprises programming the one memory cell of the pair of gate-connected non-volatile memory cells if the information indicative of the data value stored in the particular memory cell has a logic low level, and programming the other memory cell of the pair of gate-connected non-volatile memory cells if the information indicative of the data value stored in the particular memory cell has a logic high level.

8. The method of claim 1 , wherein selectively programming the one memory cell of the pair of gate-connected non-volatile memory cells responsive to the information indicative of the data value stored in the particular memory cell if a power loss is indicated comprises programming the one memory cell of the pair of gate-connected non-volatile memory cells only if the information indicative of the data value stored in the particular memory cell has a particular logic level, and programming neither memory cell of the pair of gate-connected non-volatile memory cells if the information indicative of the data value stored in the particular memory cell has a different logic level.

9. The method of claim 8 , wherein the resulting combination of threshold voltages of the one memory cell of the pair of gate-connected non-volatile memory cells and of the other memory cell of the pair of gate-connected non-volatile memory cells resulting in the one memory cell being deactivated in response to a particular gate voltage and the other memory cell being activated in response to the particular gate voltage is representative of the information indicative of the data value stored in the particular memory cell having the particular logic level, and wherein the resulting combination of threshold voltages of the one memory cell of the pair of gate-connected non-volatile memory cells and of the other memory cell of the pair of gate-connected non-volatile memory cells resulting in the one memory cell being activated in response to the particular gate voltage is representative of the information indicative of the data value stored in the particular memory cell having the different logic level.

10. The method of claim 9 , wherein the resulting combination of threshold voltages of the one memory cell of the pair of gate-connected non-volatile memory cells and of the other memory cell of the pair of gate-connected non-volatile memory cells resulting in the one memory cell and the other memory cell being activated in response to the particular gate voltage is representative of the information indicative of the data value stored in the particular memory cell having the different logic level.

11. The method of claim 9 , wherein the resulting combination of threshold voltages of the one memory cell of the pair of gate-connected non-volatile memory cells and of the other memory cell of the pair of gate-connected non-volatile memory cells resulting in the one memory cell being activated in response to the particular gate voltage and the other memory cell being deactivated in response to the particular gate voltage is representative of the information indicative of the data value stored in the particular memory cell having the different logic level.

12. The method of claim 1 , wherein determining if a power loss to the memory is indicated while programming the additional data to the particular memory cell comprises determining if a voltage level of a supply voltage of the memory falls below a threshold.

13. The method of claim 12 , wherein the threshold is below a specified range of desired voltage levels for the supply voltage.

14. The method of claim 12 , wherein the threshold is within a specified range of desired voltage levels for the supply voltage.

15. A method of operating a memory, comprising:

obtaining information indicative of a data value stored in a particular memory cell of the memory;

programming additional data to the particular memory cell;

determining if a power loss to the memory is indicated while programming the additional data to the particular memory cell comprising determining if a voltage level of a supply voltage of the memory falls below a threshold; and

if a power loss to the memory is indicated, selectively programming one memory cell of a pair of gate-connected non-volatile memory cells responsive to the information indicative of the data value stored in the particular memory cell comprising programming the one memory cell of the pair of gate-connected non-volatile memory cells if the information indicative of the data value stored in the particular memory cell has a first logic level, and inhibiting programming of the one memory cell of the pair of gate-connected non-volatile memory cells if the information indicative of the data value stored in the particular memory cell has a second logic level different than the first logic level;

wherein a resulting combination of threshold voltages of the one memory cell of the pair of gate-connected non-volatile memory cells and of the other memory cell of the pair of gate-connected non-volatile memory cells is representative of the information indicative of the data value stored in the particular memory cell.

16. The method of claim 15 , further comprising selectively programming the other memory cell of the pair of gate-connected non-volatile memory cells responsive to the information indicative of the data value stored in the particular memory cell.

17. The method of claim 16 , wherein selectively programming the other memory cell of the pair of gate-connected non-volatile memory cells responsive to the information indicative of the data value stored in the particular memory cell comprises programming the other memory cell of the pair of gate-connected non-volatile memory cells if the information indicative of the data value stored in the particular memory cell has the second logic level, and inhibiting programming of the other memory cell of the pair of gate-connected non-volatile memory cells if the information indicative of the data value stored in the particular memory cell has the first logic level.

18. The method of claim 15 , wherein selectively programming the one memory cell of the pair of gate-connected non-volatile memory cells responsive to the information indicative of the data value stored in the particular memory cell comprises:

applying a first voltage level to a first source/drain of the one memory cell of the pair of gate-connected non-volatile memory cells and to a first source/drain of the other memory cell of the pair of gate-connected non-volatile memory cells;

applying a second voltage level higher than the first voltage level to a gate of the one memory cell of the pair of gate-connected non-volatile memory cells and to a gate of the other memory cell of the pair of gate-connected non-volatile memory cells;

applying a third voltage level, higher than the first voltage level and lower than the second voltage level, to a second source/drain of the one memory cell of the pair of gate-connected non-volatile memory cells; and

applying the first voltage level to a second source/drain of the other memory cell of the pair of gate-connected non-volatile memory cells.

19. The method of claim 18 , wherein a combination of the first voltage level, the second voltage level and the third voltage level is selected to cause charge to accumulate in a data-storage structure of the one memory cell during programming of the one memory cell, and to inhibit charge accumulation in a data-storage structure of the other memory cell during programming of the one memory cell.

20. The method of claim 15 , wherein the threshold is either below a specified range of desired voltage levels for the supply voltage, or within the specified range of desired voltage levels for the supply voltage.