IP Library Granted Patent US 10,678,927
Granted Patent B2
US 10,678,927 · App. 15/692,171 · Granted Jun 9, 2020

Randomized execution countermeasures against fault injection attacks during boot of an embedded device

Inventors: Madan Srinivas (Gaithersburg, MD); Sachin Billore (Bangalore, IN); Kavitha Malarvizhi (Bangalore, IN); Amritpal Mundra (Allen, TX)
Assignee: TEXAS INSTRUMENTS INCORPORATED
G06F21/575G06F1/24G06F9/4401G06F21/566G06F2221/034
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Quick Facts
Patent No.
US 10,678,927
App. No.
15/692,171
Granted
Jun 9, 2020
Kind
B2
Abstract

An embedded device is provided that is configured to randomize execution time of a boot process of the embedded device performed responsive to a reset signal, wherein reset release time is nondeterministic. The embedded device may include a randomizer component configured to generate a timeout signal after a random interval, wherein to randomize execution time, the embedded device is further configured to execute a first portion of a reset process, signal the randomizer component to generate the timeout signal after a first random interval, wait for the timeout signal, and execute a second portion of the reset process responsive to the timeout signal.

Claims (31)

1. An embedded device, comprising:

a randomizer component configured to generate a timeout signal after a random interval, and

a control component configured to execute a portion of a reset process, pause the reset process and signal the randomizer component to generate the timeout signal after a first random interval, wait for the timeout signal to be generated, and continue the reset process after the timeout signal is detected.

2. The embedded device of claim 1 , wherein a reset process of the boot process is a power on reset process.

3. The embedded device of claim 1 , further comprising a hardware random number generator, and wherein the randomizer component comprises timer circuitry and circuitry to initialize the hardware random number generator and to obtain a random number from the hardware random number generator to seed the timer circuitry.

4. The embedded device of claim 1 , wherein the embedded device is further configured to signal the randomizer component to generate the timeout signal after a second random interval after a second portion is executed.

5. The embedded device of claim 1 , further comprising:

a boot read-only-memory (ROM) configured to store boot code, wherein initiation of execution of the boot code after reset release is randomized.

6. The embedded device of claim 5 , wherein the boot code comprises a random delay between a first boot code function and a second boot code function, wherein execution time of a security function is nondeterministic.

7. The embedded device of claim 6 , wherein the random delay is implemented as a delay loop that is executed for a randomly selected number of times.

8. The embedded device of claim 6 , wherein the boot code is configured to randomize an order of execution of independent boot functions.

9. The embedded device of claim 1 , further comprising a control component coupled to the randomizer component and configured to signal the randomizer component to start operation at selected points in the reset process.

10. A method for randomizing execution time of a boot process of an embedded device, the method comprising:

receiving a reset signal in the embedded device;

executing a portion of a reset process of the boot process responsive to the reset signal;

generating a random timeout signal after a random interval after executing the portion;

waiting for the timeout signal; and

resuming executing a remaining portion of the reset process responsive to the timeout signal.

11. The method of claim 10 , further comprising:

generating the random timeout signal after a second random interval after continuing executing the portion.

12. The method of claim 10 , wherein the reset process is a power on reset process.

13. The method of claim 10 , further comprising initializing a hardware random number generator comprised in the embedded device and seeding timer circuitry based on a random number obtained from the hardware random number generator.

14. The method of claim 10 , further comprising randomizing initiation of execution of boot code after reset release.

15. The method of claim 14 , further comprising executing a random delay between a first boot code function and a second boot code function, wherein execution time of a security function is nondeterministic.

16. The method of claim 15 , wherein the random delay is implemented as a delay loop that is executed for a randomly selected number of times.

17. The method of claim 15 , further comprising randomizing an order of execution of independent boot functions.

18. An embedded device, comprising:

a randomizer component configured to generate a timeout signal after a random interval;

a control component configured to signal the randomizer component to start operation at selected points in a reset process of the embedded device, wherein time of reset release time is nondeterministic; and

a boot read-only-memory (ROM) configured to store a plurality of boot codes for the reset process, wherein initiation of the reset process includes executing a first boot code after the reset release, which is randomized, the reset process comprises a random delay between executing the first boot code and executing a second boot code such that execution time of the reset process is nondeterministic.

19. The embedded device of claim 18 , further comprising a hardware random number generator, and wherein the randomizer component comprises timer circuitry and circuitry to initialize the hardware random number generator and to obtain a random number from the hardware random number generator to seed the timer circuitry.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 31, 2017
From: SRINIVAS, MADAN; BILLORE, SACHIN; MALARVIZHI, KAVITHA; MUNDRA, AMRITPAL
To: TEXAS INSTRUMENTS INCORPORATED
Reel/Frame 043463/0769 →
Continuity (1)
Related Publication 20190065751A1 · Feb 28, 2019
Cited By (1)
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