IP Library Granted Patent US 10,831,384
Granted Patent B2
US 10,831,384 · App. 15/692,553 · Granted Nov 10, 2020

Memory device with power management

Inventors: Brock Myers (Longmont, CO); Carl Mies (Federick, CO)
Assignee: Micron Technology, Inc.
G06F3/0625G06F1/3225G06F3/0659G06F3/0679G06F3/0688
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Quick Facts
Patent No.
US 10,831,384
App. No.
15/692,553
Granted
Nov 10, 2020
Kind
B2
Abstract

A memory device includes a memory array including a plurality of memory components; and a controller coupled to the memory array, the controller configured to: determine a set of transactions to be implemented across two or more memory components according to an initial schedule; calculate a first plurality of power consumption levels corresponding to the initial schedule; and if one or more of the power consumption levels exceed a predetermined threshold, calculate an updated schedule for implementing the set of transactions across the two or more memory components, wherein the updated schedule corresponds to a second plurality of power consumption levels that are all at or below the predetermined threshold.

Claims (57)

1. A memory device, comprising:

a memory array including a plurality of memory components; and

a memory controller coupled to the memory array, the controller configured to:

determine a set of transactions to be implemented across two or more memory components according to an initial schedule, wherein the transactions are associated with transient load spikes that each correspond to a local or an overall maximum load level lasting for less than a threshold duration for a corresponding transaction in the set of transactions;

identify two or more load profiles that correspond to the set of transactions, the two or more load profiles each representing a sequence of power consumption levels that correspond to a sampling frequency, wherein subsets of values in the two or more load profiles correspond to the transient load spikes;

calculate a first plurality of power consumption levels corresponding to the initial schedule based on summing values in the identified load profiles across the two or more memory components, wherein the first plurality of power consumption levels includes summed values corresponding to the transient load spikes; and

when one or more levels in the first plurality of power consumption levels exceed a predetermined threshold, calculate an updated schedule based on (1) dynamically shifting one or more of the identified load profiles to an upcoming instance of time slots, wherein the time slots correspond to the sampling frequency, and (2) evaluating a sum of power consumption level sequences for the identified load profiles within the upcoming instance of the time slots, the updated schedule for implementing the set of transactions across the two or more memory components, wherein:

the one or more levels in the first plurality of power consumption levels that exceed the predetermined threshold corresponds to a time when one or more of the transient load spikes are scheduled to occur according to the initial schedule, and

the updated schedule corresponds to a second plurality of power consumption levels that are all at or below the predetermined threshold.

2. The memory device of claim 1 wherein the load profiles each include a sequence sampled power values representative of different power consumption levels, including the transient load spikes, sampled at the sampling frequency during a previous execution of a representative transaction of a same type.

3. The memory device of claim 2 wherein the memory controller is configured to:

calculate the first plurality of power consumption levels based on calculating a combined consumption by adding the sampled values of the load profiles corresponding to transactions in the initial schedule; and

calculate the updated schedule based on determining that one or more levels in the first plurality of power consumption levels exceed the predetermined threshold by comparing the combined consumption at upcoming time slots to the predetermined threshold.

4. The memory device of claim 1 wherein the memory controller is configured to:

receive the set of transactions or a portion thereof from a host device, wherein the set of transactions or the portion thereof are received according to an incoming sequence; and

calculate the updated schedule different than the incoming sequence.

5. The memory device of claim 4 wherein the memory controller is configured to:

receive the set of transactions including a first transaction received before a second transaction; and

calculate the updated schedule for implementing the second transaction before the first transaction based on upcoming power utilization needs.

6. The memory device of claim 4 wherein the memory controller is configured to:

receive the set of transactions including a transaction designated for implementation with a memory component; and

calculate the updated schedule including implementing the transaction with a different memory component.

7. The memory device of claim 4 wherein the memory controller is configured to:

receive the set of transactions including a transaction; and

calculate the updated schedule including a first timing, a second timing, and a third timing, the first timing for initiating the transaction, the second timing for suspending the transaction after initiation, and the third timing for resuming the transaction after suspension.

8. The memory device of claim 1 wherein the memory controller is configured to calculate the updated schedule according to transaction types.

9. The memory device of claim 8 wherein the memory controller is configured to delay or suspend a write operation or an erase operation before adjusting a timing for a read operation.

10. The memory device of claim 1 wherein the load profiles each corresponds to a set of measurements taken during g execution of a corresponding transaction type implemented on one memory component for the memory device, wherein each of the load profiles is for representing subsequent executions for the corresponding transaction type implemented on the memory components within the memory device.

11. The memory device of claim 1 wherein the controller is configured to reschedule the set of transactions within an operation stack.

12. The memory device of claim 1 wherein the memory components are NAND dies.

13. The memory device of claim 1 further comprising:

a power circuitry, coupled to the controller, configured to provide filtered power to the memory array and the controller; and wherein:

the load profiles each represent the sequence of power consumption level corresponding to the filtered power.

14. The memory device of claim 1 wherein the updated schedule includes concurrent implementation of two or more transactions.

15. A method of operating a memory device including a controller and a memory array including memory components, the method comprising:

determining a set of transactions to be implemented across two or more memory components according to an initial schedule, wherein the transactions are associated with transient load spikes that each correspond to a local or an overall maximum load level lasting for less than a threshold duration for a corresponding transaction in the set of transactions;

identifying two or more load profiles that correspond to the set of transactions, the two or more load profiles each representing a sequence of power consumption levels that correspond to a sampling frequency, wherein subsets of values in the two or more load profiles correspond to the transient load spikes;

estimating a first plurality of power consumption levels corresponding to the initial schedule based on summing power consumption levels of the identified load profiles across the two or more memory components, wherein the first plurality of power consumption levels includes summed values corresponding to the transient load spikes of the set of transactions; and

when one or more levels in the first plurality of power consumption levels exceed a predetermined threshold, calculating an updated schedule based on (1) dynamically shifting one or more of the identified load profiles to an upcoming instance of time slots, wherein the time slots correspond to the sampling frequency, and (2) evaluating a sum of power consumption level sequences for the identified load profiles within the upcoming instance of the time slots, the updated schedule for implementing the set of transactions across the two or more memory components, wherein:

the one or more levels in the first plurality of power consumption levels that exceed the predetermined threshold corresponds to a time when one or more of the transient load spikes are scheduled to occur according to the initial schedule, and

the updated schedule corresponds to a second plurality of power consumption levels that are all at or below the predetermined threshold.

16. The method of claim 15 , wherein the load profiles each include a sequence of sampled power values, including the transient load spikes, representing the sequence of power consumption level sampled at a sampling frequency during previous execution of the corresponding transaction.

17. The method of claim 16 , wherein:

estimating the first plurality of power consumption levels includes calculating a combined consumption by adding the sampled values of the load profiles corresponding to transactions in the initial schedule; and

calculating the updated schedule includes determining that one or more levels in the first plurality of power consumption levels exceed the predetermined threshold based on comparing the combined consumption at upcoming time slots to the predetermined threshold.

18. The method of claim 15 , further comprising:

receiving the set of transactions or a portion thereof from a host device, wherein the set of transactions or the portion thereof are received according to an incoming sequence; and

wherein calculating the updated schedule includes calculating the updated schedule that is different than the incoming sequence.

19. The method of claim 15 , wherein:

receiving the set of transactions or a portion thereof includes receiving a first transaction and a second transaction, wherein the first transaction is intended for implementation on a particular component before the second transaction according to the incoming sequence; and

wherein calculating the updated schedule includes calculating the updated schedule for implementing the second transaction before the first transaction, for implementing the first transaction on a different component, for suspending one of the transactions while implementing the other transaction, or a combination thereof based on upcoming power utilization needs.

20. The method of claim 15 , further comprising:

executing a read operation, a write operation, or an erase operation;

dynamically measuring power consumption levels during execution of the read operation, the write operation, or the erase operation; and

generating a load profile for the executed one of the operations based on the measured power consumption levels, the sequence of power consumption levels.

21. The memory device of claim 1 wherein lengths of different load profiles are independent of each other and correspond to an execution duration of a corresponding type of transaction.

22. The memory device of claim 1 wherein dynamically shifting the two or more of the identified load profiles comprises shifting one or more portions thereof.

Assignments (7)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050709/0838 →
RELEASE OF SECURITY INTEREST Recorded Jul 20, 2018
From: U.S. BANK NATIONAL ASSOCIATION, AS AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 046597/0333 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 23, 2018
From: MYERS, BROCK; MIES, CARL
To: MICRON TECHNOLOGY, INC.
Reel/Frame 044700/0929 →
SUPPLEMENT NO. 6 TO PATENT SECURITY AGREEMENT Recorded Nov 1, 2017
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 044348/0253 →
SUPPLEMENT NO. 6 TO PATENT SECURITY AGREEMENT Recorded Nov 1, 2017
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 044653/0333 →
Continuity (1)
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