Stage circuit and scan driver using the same

1. A stage circuit, comprising:

an input unit configured to control voltages of a first node and a second node, both first and second nodes contained in the input unit, by using a shift pulse or a gate start pulse input to a first input terminal, a first clock signal input to a second input terminal, a second clock signal input to a third input terminal, a first power supply input to a first power supply input terminal, and a second power supply input to a second power supply input terminal; and

a first output unit configured to receive a third clock signal from a fourth input terminal and the second power supply from the second power supply input terminal, and to output a high-level scan signal to a first output terminal corresponding to the voltages of the first node and the second node,

wherein:

a width of the high-level scan signal is the same as a width of a high level of the third clock signal and different from a width of a low level of each of the first and second clock signals; and

the low level of each of the first and second clock signals is a gate-on voltage to turn on a transistor.

2. The stage circuit of claim 1 , wherein:

in response to an ith (i is a natural number) stage circuit being set to a first stage, the gate start pulse is supplied to the first input terminal; and

otherwise, the shift pulse is supplied from an (i−1)th stage to the first input terminal.

3. The stage circuit of claim 1 , wherein the first clock signal, the second clock signal, and the third clock signal have a same cycle.

4. The stage circuit of claim 3 , wherein the first clock signal and the second clock signal have a duty ratio of 50%, and the second clock signal is set to a signal obtained by inverting the first clock signal.

5. The stage circuit of claim 4 , wherein the third clock signal is set to the high level during a first period of one cycle and set to a low level during a second period longer than the first period.

6. The stage circuit of claim 5 , wherein a high-level period of the third clock signal overlaps a high-level period of the first clock signal.

7. The stage circuit of claim 1 , wherein the first power supply is set to a gate-off voltage, and the second power supply is set to the gate-on voltage.

8. The stage circuit of claim 1 , wherein the first output unit comprises:

a first transistor connected between the fourth input terminal and the first output terminal and comprising a gate electrode connected to the first node;

a second transistor connected between the first output terminal and the second power supply input terminal and comprising a gate electrode connected to the second node; and

a first capacitor connected between the second node and the first output terminal.

9. The stage circuit of claim 1 , wherein the input unit comprises:

a third transistor connected between the first power supply input terminal and a third node and comprising a gate electrode connected to the second input terminal;

a fourth transistor connected between the third node and the third input terminal and comprising a gate electrode connected to a fourth node;

a fifth transistor connected between the fourth node and the first input terminal and comprising a gate electrode connected to the second input terminal;

a sixth transistor connected between the first power supply input terminal and the second node and comprising a gate electrode connected to the third node;

a seventh transistor connected between the second node and the second power supply input terminal and comprising a gate electrode connected to the second input terminal;

an eighth transistor connected between the first power supply input terminal and the first node and comprising a gate electrode connected to the second node;

a ninth transistor connected between the first node and the second power supply input terminal and comprising a gate electrode connected to the third node; and

a second capacitor connected between the third node and the fourth node.

10. The stage circuit of claim 9 , wherein the input unit is configured to supply a voltage of the third node or the voltage of the first node as the shift pulse to a subsequent stage.

11. The stage circuit of claim 9 , further comprising a second output unit configured to receive a fifth clock signal from a fifth input terminal and the first power supply from the first power supply input terminal, and to output a low-level scan signal to a second output terminal corresponding to the voltage of the second node and a voltage of the fourth node.

12. The stage circuit of claim 11 , wherein the fifth clock signal is set to a signal obtained by inverting the third clock signal.

13. The stage circuit of claim 11 , wherein the second output unit comprises:

a tenth transistor connected between the first power supply input terminal and the second output terminal and comprising a gate electrode connected to the second node;

an eleventh transistor connected between the second output terminal and the fifth input terminal and comprising a gate electrode connected to a fifth node;

a twelfth transistor connected between the fourth node and the fifth node and comprising a gate electrode connected to the fifth input terminal;

a third capacitor connected between the fifth node and the second output terminal; and

a fourth capacitor connected between the first power supply input terminal and the second node.

14. A scan driver, comprising a plurality of stages configured to supply a low-level first scan signal to a first scan line and a high-level second scan signal to a second scan line,

wherein:

an ith (i is a natural number) stage comprises:

an input unit configured to control voltages of a first node and a second node, both first and second nodes contained in the input unit, by using a shift pulse or a gate start pulse input to a first input terminal, a first clock signal input to a second input terminal, a second clock signal input to a third input terminal, a first power supply input to a first power supply input terminal, and a second power supply input to a second power supply input terminal;

a first output unit configured to receive a third clock signal from a fourth input terminal and the second power supply from the second power supply input terminal, and to output the second scan signal to a first output terminal corresponding to the voltages of the first node and the second node; and

a second output unit configured to receive a fifth clock signal from a fifth input terminal and the first power supply from the first power supply input terminal, and to output the first scan signal to a second output terminal corresponding to the voltage of the second node;

the first output unit and the second output unit simultaneously output the high-level second scan signal and the low-level first scan signal, respectively; and

a width of the high-level second scan signal is substantially the same as a width of the low-level first scan signal.

15. The scan driver of claim 14 , wherein:

in response to the ith stage being set to a first stage, a gate start pulse is input to the first input terminal; and

otherwise, the shift pulse is input from an (i−1)th stage.

16. The scan driver of claim 14 , wherein the first clock signal, the second clock signal, the third clock signal, and the fifth clock signal have a same cycle.

17. The scan driver of claim 16 , wherein the first clock signal and the second clock signal have a duty ratio of 50%, and the second clock signal is set to a signal obtained by inverting the first clock signal.

18. The scan driver of claim 17 , wherein the third clock signal is set to a high level during a first period of one cycle, and set to a low level during a second period longer than the first period.

19. The scan driver of claim 18 , wherein a high-level period of the third clock signal overlaps a high-level period of the first clock signal.

20. The scan driver of claim 18 , wherein the fifth clock signal is set to a signal obtained by inverting the third clock signal.

21. The scan driver of claim 16 , wherein the second clock signal is input to a second input terminal, the first clock signal is input to a third input terminal, a fourth clock signal is input to a fourth input terminal, and a sixth clock signal is input to a fifth input terminal of an (i+1)th stage circuit.

22. The scan driver of claim 21 , wherein the fourth clock signal is set to a high level during a first period of one cycle, and set to a low level during a second period longer than the first period.

23. The scan driver of claim 22 , wherein a high-level period of the fourth clock signal overlaps a high-level period of the second clock signal.

24. The scan driver of claim 22 , wherein the sixth clock signal is set to a signal obtained by inverting the fourth clock signal.

25. The scan driver of claim 14 , wherein the first power supply is set to a gate-off voltage, and the second power supply is set to a gate-on voltage.

26. The scan driver of claim 14 , wherein the first output unit comprises:

a first transistor connected between the fourth input terminal and the first output terminal and comprising a gate electrode connected to the first node;

a second transistor connected between the first output terminal and the second power supply input terminal and comprising a gate electrode connected to the second node; and

a first capacitor connected between the second node and the first output terminal.

27. The scan driver of claim 14 , wherein the input unit comprises:

a third transistor connected between the first power supply input terminal and a third node and comprising a gate electrode connected to the second input terminal;

a fourth transistor connected between the third node and the third input terminal and comprising a gate electrode connected to a fourth node;

a fifth transistor connected between the fourth node and the first input terminal and comprising a gate electrode connected to the second input terminal;

a sixth transistor connected between the first power supply input terminal and the second node and comprising a gate electrode connected to the third node;

a seventh transistor connected between the second node and the second power supply input terminal and comprising a gate electrode connected to the second input terminal;

an eighth transistor connected between the first power supply input terminal and the first node and comprising a gate electrode connected to the second node;

a ninth transistor connected between the first node and the second power supply input terminal and comprising a gate electrode connected to the third node; and

a second capacitor connected between the third node and the fourth node.

28. The scan driver of claim 27 , wherein the input unit is configured to supply a voltage of the third node or the voltage of the first node as the shift pulse to a subsequent stage.

29. The scan driver of claim 27 , wherein the second output unit comprises:

a tenth transistor connected between the first power supply input terminal and the second output terminal and comprising a gate electrode connected to the second node;

an eleventh transistor connected between the second output terminal and the fifth input terminal and comprising a gate electrode connected to a fifth node;

a twelfth transistor connected between the fourth node and the fifth node and comprising a gate electrode connected to the fifth input terminal;

a third capacitor connected between the fifth node and the second output terminal; and

a fourth capacitor connected between the first power supply input terminal and the second node.