Method for Solder Bridging Elimination for Bulk Solder C2S Interconnects
A semiconductor device assembly that includes a semiconductor device positioned over a substrate with a number of electrical interconnections formed between the semiconductor device and the substrate. The surface of the substrate includes a plurality of discrete solder mask standoffs that extend towards the semiconductor device. A thermal compression bonding process is used to melt solder to form the electrical interconnects, which lowers the semiconductor device to contact and be supported by the plurality of discrete solder mask standoffs. The solder mask standoffs permit the application of a higher pressure during the bonding process than using traditional solder masks. The solder mask standoffs may have various polygonal or non-polygonal shapes and may be positioned in pattern to protect sensitive areas of the semiconductor device and/or the substrate. The solder mask standoffs may be an elongated shape that protects areas of the semiconductor device and/or substrate.
1 . A semiconductor device assembly comprising:
a substrate having at least one discrete solder mask standoff, the at least one discrete solder mask standoff being positioned on an electrical trace;
a semiconductor device disposed over the substrate, the semiconductor device having at least one pillar that extends from the semiconductor device towards the substrate and the at least one discrete solder mask standoff extends from the substrate towards the semiconductor device; and
wherein solder connects the at least one pillar to a trace on the substrate and wherein the at least one discrete solder mask standoff supports the semiconductor device disposed over the substrate.
2 . The assembly of claim 1 , wherein the at least one discrete solder mask standoff has a thickness of approximately 15 microns and the electrical trace having a thickness of approximately 15 microns.
3 . The assembly of claim 1 , wherein the at least one discrete solder mask standoff has an elongated shape.
4 . The assembly of claim 3 , wherein a major axis of the elongated shape is substantially parallel with an edge of the substrate.
5 . The assembly of claim 3 , wherein a major axis of the elongated shape is substantially at 45 degrees with respect to an edge of the substrate.
6 . A semiconductor device assembly comprising:
a substrate having a plurality of discrete solder mask standoffs, each of the plurality of discrete solder mask standoffs being positioned on an electrical trace;
a semiconductor device positioned adjacent to the substrate; and
a plurality of electrical interconnects between the substrate and the semiconductor device;
wherein the plurality of discrete solder mask standoffs extend from the substrate and contact a bottom surface of the semiconductor device.
7 . The assembly of claim 6 , wherein the plurality of discrete solder mask standoffs are arranged in a predetermined pattern on the substrate.
8 . The assembly of claim 6 , wherein the plurality of solder mask standoffs cover less than 50% of a surface of the substrate.
9 . The assembly of claim 6 , wherein each of the discrete solder mask standoffs have a thickness between 5 microns and 100 microns.
10 . The assembly of claim 6 , wherein a horizontal cross-sectional shape of the discrete solder mask standoffs is polygonal is shape.
11 . The assembly of claim 6 , wherein a horizontal cross-sectional shape of the discrete solder mask standoffs is circular or elliptical in shape.
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21 . The assembly of claim 1 , wherein the electrical trace is electrically isolated.
22 . The assembly of claim 1 , wherein solder connects the at least one pillar to the trace on the substrate via a pad.
23 . The assembly of claim 22 , the substrate having a plurality of exposed traces positioned in a middle of the substrate, wherein the pad is an outlaying pad positioned away from the exposed traces positioned in the middle of the substrate.
24 . The assembly of claim 6 , wherein each of the electrical traces positioned under each discrete solder mask standoff is electrically isolated.
25 . The assembly of claim 6 , wherein the plurality of electrical interconnects each comprises a pillar connected to a pad via solder.
26 . The assembly of claim 25 , the substrate having a plurality of exposed traces positioned in a middle of the substrate, wherein at least one pad of the plurality of interconnects is an outlaying pad positioned away from the exposed traces positioned in the middle of the substrate.